socfpga_arria10_socdk_sdmmc_handoff.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright (C) 2016-2017 Intel Corporation
  4. *
  5. *<auto-generated>
  6. * This code was generated by a tool based on
  7. * handoffs from both Qsys and Quartus.
  8. *
  9. * Changes to this file may be lost if
  10. * the code is regenerated.
  11. *</auto-generated>
  12. */
  13. #include "socfpga_arria10.dtsi"
  14. / {
  15. model = "Altera SOCFPGA Arria 10";
  16. compatible = "altr,socfpga-arria10", "altr,socfpga";
  17. chosen {
  18. /* Bootloader setting: uboot.rbf_filename */
  19. cff-file = "ghrd_10as066n2.periph.rbf";
  20. early-release-fpga-config;
  21. };
  22. soc {
  23. u-boot,dm-pre-reloc;
  24. clkmgr@ffd04000 {
  25. u-boot,dm-pre-reloc;
  26. clocks {
  27. u-boot,dm-pre-reloc;
  28. osc1 {
  29. u-boot,dm-pre-reloc;
  30. clock-frequency = <25000000>;
  31. clock-output-names = "altera_arria10_hps_eosc1-clk";
  32. };
  33. cb_intosc_ls_clk {
  34. u-boot,dm-pre-reloc;
  35. clock-frequency = <60000000>;
  36. clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
  37. };
  38. f2s_free_clk {
  39. u-boot,dm-pre-reloc;
  40. clock-frequency = <200000000>;
  41. clock-output-names = "altera_arria10_hps_f2h_free-clk";
  42. };
  43. main_pll {
  44. u-boot,dm-pre-reloc;
  45. /*
  46. * Address Block: soc_clock_manager_OCP_SLV.
  47. * i_clk_mgr_mainpllgrp
  48. */
  49. altr,of_reg_value = <
  50. 0 /* Field: vco0.psrc */
  51. 1 /* Field: vco1.denom */
  52. 191 /* Field: vco1.numer */
  53. 0 /* Field: mpuclk */
  54. 0 /* Field: mpuclk.cnt */
  55. 0 /* Field: mpuclk.src */
  56. 0 /* Field: nocclk */
  57. 0 /* Field: nocclk.cnt */
  58. 0 /* Field: nocclk.src */
  59. 900 /* Field: cntr2clk.cnt */
  60. 900 /* Field: cntr3clk.cnt */
  61. 900 /* Field: cntr4clk.cnt */
  62. 900 /* Field: cntr5clk.cnt */
  63. 900 /* Field: cntr6clk.cnt */
  64. 900 /* Field: cntr7clk.cnt */
  65. 0 /* Field: cntr7clk.src */
  66. 900 /* Field: cntr8clk.cnt */
  67. 900 /* Field: cntr9clk.cnt */
  68. 0 /* Field: cntr9clk.src */
  69. 900 /* Field: cntr15clk.cnt */
  70. 0 /* Field: nocdiv.l4mainclk */
  71. 0 /* Field: nocdiv.l4mpclk */
  72. 2 /* Field: nocdiv.l4spclk */
  73. 0 /* Field: nocdiv.csatclk */
  74. 1 /* Field: nocdiv.cstraceclk */
  75. 1 /* Field: nocdiv.cspdbgclk */
  76. >;
  77. };
  78. periph_pll {
  79. u-boot,dm-pre-reloc;
  80. /*
  81. * Address Block: soc_clock_manager_OCP_SLV.
  82. * i_clk_mgr_perpllgrp
  83. */
  84. altr,of_reg_value = <
  85. 0 /* Field: vco0.psrc */
  86. 1 /* Field: vco1.denom */
  87. 159 /* Field: vco1.numer */
  88. 7 /* Field: cntr2clk.cnt */
  89. 1 /* Field: cntr2clk.src */
  90. 900 /* Field: cntr3clk.cnt */
  91. 1 /* Field: cntr3clk.src */
  92. 19 /* Field: cntr4clk.cnt */
  93. 1 /* Field: cntr4clk.src */
  94. 499 /* Field: cntr5clk.cnt */
  95. 1 /* Field: cntr5clk.src */
  96. 9 /* Field: cntr6clk.cnt */
  97. 1 /* Field: cntr6clk.src */
  98. 900 /* Field: cntr7clk.cnt */
  99. 900 /* Field: cntr8clk.cnt */
  100. 0 /* Field: cntr8clk.src */
  101. 900 /* Field: cntr9clk.cnt */
  102. 0 /* Field: emacctl.emac0sel */
  103. 0 /* Field: emacctl.emac1sel */
  104. 0 /* Field: emacctl.emac2sel */
  105. 32000 /* Field: gpiodiv.gpiodbclk */
  106. >;
  107. };
  108. altera {
  109. u-boot,dm-pre-reloc;
  110. /*
  111. * Address Block: soc_clock_manager_OCP_SLV.
  112. * i_clk_mgr_alteragrp
  113. */
  114. altr,of_reg_value = <
  115. 0x0384000b /* Register: nocclk */
  116. 0x03840001 /* Register: mpuclk */
  117. >;
  118. };
  119. };
  120. };
  121. /*
  122. * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
  123. * Binding: pinmux
  124. */
  125. i_io48_pin_mux: pinmux@0xffd07000 {
  126. u-boot,dm-pre-reloc;
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. compatible = "pinctrl-single";
  130. reg = <0xffd07000 0x00000800>;
  131. reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
  132. /*
  133. * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
  134. * i_io48_pin_mux_shared_3v_io_grp
  135. */
  136. shared {
  137. u-boot,dm-pre-reloc;
  138. reg = <0xffd07000 0x00000200>;
  139. pinctrl-single,register-width = <32>;
  140. pinctrl-single,function-mask = <0x0000000f>;
  141. pinctrl-single,pins =
  142. /* Reg: pinmux_shared_io_q1_1 */
  143. <0x00000000 0x00000008>,
  144. /* Reg: pinmux_shared_io_q1_2 */
  145. <0x00000004 0x00000008>,
  146. /* Reg: pinmux_shared_io_q1_3 */
  147. <0x00000008 0x00000008>,
  148. /* Reg: pinmux_shared_io_q1_4 */
  149. <0x0000000c 0x00000008>,
  150. /* Reg: pinmux_shared_io_q1_5 */
  151. <0x00000010 0x00000008>,
  152. /* Reg: pinmux_shared_io_q1_6 */
  153. <0x00000014 0x00000008>,
  154. /* Reg: pinmux_shared_io_q1_7 */
  155. <0x00000018 0x00000008>,
  156. /* Reg: pinmux_shared_io_q1_8 */
  157. <0x0000001c 0x00000008>,
  158. /* Reg: pinmux_shared_io_q1_9 */
  159. <0x00000020 0x00000008>,
  160. /* Reg: pinmux_shared_io_q1_10 */
  161. <0x00000024 0x00000008>,
  162. /* Reg: pinmux_shared_io_q1_11 */
  163. <0x00000028 0x00000008>,
  164. /* Reg: pinmux_shared_io_q1_12 */
  165. <0x0000002c 0x00000008>,
  166. /* Reg: pinmux_shared_io_q2_1 */
  167. <0x00000030 0x00000004>,
  168. /* Reg: pinmux_shared_io_q2_2 */
  169. <0x00000034 0x00000004>,
  170. /* Reg: pinmux_shared_io_q2_3 */
  171. <0x00000038 0x00000004>,
  172. /* Reg: pinmux_shared_io_q2_4 */
  173. <0x0000003c 0x00000004>,
  174. /* Reg: pinmux_shared_io_q2_5 */
  175. <0x00000040 0x00000004>,
  176. /* Reg: pinmux_shared_io_q2_6 */
  177. <0x00000044 0x00000004>,
  178. /* Reg: pinmux_shared_io_q2_7 */
  179. <0x00000048 0x00000004>,
  180. /* Reg: pinmux_shared_io_q2_8 */
  181. <0x0000004c 0x00000004>,
  182. /* Reg: pinmux_shared_io_q2_9 */
  183. <0x00000050 0x00000004>,
  184. /* Reg: pinmux_shared_io_q2_10 */
  185. <0x00000054 0x00000004>,
  186. /* Reg: pinmux_shared_io_q2_11 */
  187. <0x00000058 0x00000004>,
  188. /* Reg: pinmux_shared_io_q2_12 */
  189. <0x0000005c 0x00000004>,
  190. /* Reg: pinmux_shared_io_q3_1 */
  191. <0x00000060 0x00000003>,
  192. /* Reg: pinmux_shared_io_q3_2 */
  193. <0x00000064 0x00000003>,
  194. /* Reg: pinmux_shared_io_q3_3 */
  195. <0x00000068 0x00000003>,
  196. /* Reg: pinmux_shared_io_q3_4 */
  197. <0x0000006c 0x00000003>,
  198. /* Reg: pinmux_shared_io_q3_5 */
  199. <0x00000070 0x00000003>,
  200. /* Reg: pinmux_shared_io_q3_6 */
  201. <0x00000074 0x0000000f>,
  202. /* Reg: pinmux_shared_io_q3_7 */
  203. <0x00000078 0x0000000a>,
  204. /* Reg: pinmux_shared_io_q3_8 */
  205. <0x0000007c 0x0000000a>,
  206. /* Reg: pinmux_shared_io_q3_9 */
  207. <0x00000080 0x0000000a>,
  208. /* Reg: pinmux_shared_io_q3_10 */
  209. <0x00000084 0x0000000a>,
  210. /* Reg: pinmux_shared_io_q3_11 */
  211. <0x00000088 0x00000001>,
  212. /* Reg: pinmux_shared_io_q3_12 */
  213. <0x0000008c 0x00000001>,
  214. /* Reg: pinmux_shared_io_q4_1 */
  215. <0x00000090 0x00000000>,
  216. /* Reg: pinmux_shared_io_q4_2 */
  217. <0x00000094 0x00000000>,
  218. /* Reg: pinmux_shared_io_q4_3 */
  219. <0x00000098 0x0000000f>,
  220. /* Reg: pinmux_shared_io_q4_4 */
  221. <0x0000009c 0x0000000c>,
  222. /* Reg: pinmux_shared_io_q4_5 */
  223. <0x000000a0 0x0000000f>,
  224. /* Reg: pinmux_shared_io_q4_6 */
  225. <0x000000a4 0x0000000f>,
  226. /* Reg: pinmux_shared_io_q4_7 */
  227. <0x000000a8 0x0000000a>,
  228. /* Reg: pinmux_shared_io_q4_8 */
  229. <0x000000ac 0x0000000a>,
  230. /* Reg: pinmux_shared_io_q4_9 */
  231. <0x000000b0 0x0000000c>,
  232. /* Reg: pinmux_shared_io_q4_10 */
  233. <0x000000b4 0x0000000c>,
  234. /* Reg: pinmux_shared_io_q4_11 */
  235. <0x000000b8 0x0000000c>,
  236. /* Reg: pinmux_shared_io_q4_12 */
  237. <0x000000bc 0x0000000c>;
  238. };
  239. /*
  240. * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
  241. * i_io48_pin_mux_dedicated_io_grp
  242. */
  243. dedicated {
  244. u-boot,dm-pre-reloc;
  245. reg = <0xffd07200 0x00000200>;
  246. pinctrl-single,register-width = <32>;
  247. pinctrl-single,function-mask = <0x0000000f>;
  248. pinctrl-single,pins =
  249. /* Reg: pinmux_dedicated_io_4 */
  250. <0x0000000c 0x00000008>,
  251. /* Reg: pinmux_dedicated_io_5 */
  252. <0x00000010 0x00000008>,
  253. /* Reg: pinmux_dedicated_io_6 */
  254. <0x00000014 0x00000008>,
  255. /* Regi: pinmux_dedicated_io_7 */
  256. <0x00000018 0x00000008>,
  257. /* Reg: pinmux_dedicated_io_8 */
  258. <0x0000001c 0x00000008>,
  259. /* Reg: pinmux_dedicated_io_9 */
  260. <0x00000020 0x00000008>,
  261. /* Reg: pinmux_dedicated_io_10 */
  262. <0x00000024 0x0000000a>,
  263. /* Reg: pinmux_dedicated_io_11 */
  264. <0x00000028 0x0000000a>,
  265. /* Reg: pinmux_dedicated_io_12 */
  266. <0x0000002c 0x00000008>,
  267. /* Reg: pinmux_dedicated_io_13 */
  268. <0x00000030 0x00000008>,
  269. /* Reg: pinmux_dedicated_io_14 */
  270. <0x00000034 0x00000008>,
  271. /* Reg: pinmux_dedicated_io_15 */
  272. <0x00000038 0x00000008>,
  273. /* Reg: pinmux_dedicated_io_16 */
  274. <0x0000003c 0x0000000d>,
  275. /* Reg: pinmux_dedicated_io_17 */
  276. <0x00000040 0x0000000d>;
  277. };
  278. /*
  279. * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
  280. * i_io48_pin_mux_dedicated_io_grp
  281. */
  282. dedicated_cfg {
  283. u-boot,dm-pre-reloc;
  284. reg = <0xffd07200 0x00000200>;
  285. pinctrl-single,register-width = <32>;
  286. pinctrl-single,function-mask = <0x003f3f3f>;
  287. pinctrl-single,pins =
  288. /* Reg: cfg_dedicated_io_bank */
  289. <0x00000100 0x00000101>,
  290. /* Reg: cfg_dedicated_io_1 */
  291. <0x00000104 0x000b080a>,
  292. /* Reg: cfg_dedicated_io_2 */
  293. <0x00000108 0x000b080a>,
  294. /* Reg: cfg_dedicated_io_3 */
  295. <0x0000010c 0x000b080a>,
  296. /* Reg: cfg_dedicated_io_4 */
  297. <0x00000110 0x000a282a>,
  298. /* Reg: cfg_dedicated_io_5 */
  299. <0x00000114 0x000a282a>,
  300. /* Reg: cfg_dedicated_io_6 */
  301. <0x00000118 0x0008282a>,
  302. /* Reg: cfg_dedicated_io_7 */
  303. <0x0000011c 0x000a282a>,
  304. /* Reg: cfg_dedicated_io_8 */
  305. <0x00000120 0x000a282a>,
  306. /* Reg: cfg_dedicated_io_9 */
  307. <0x00000124 0x000a282a>,
  308. /* Reg: cfg_dedicated_io_10 */
  309. <0x00000128 0x00090000>,
  310. /* Reg: cfg_dedicated_io_11 */
  311. <0x0000012c 0x00090000>,
  312. /* Reg: cfg_dedicated_io_12 */
  313. <0x00000130 0x000b282a>,
  314. /* Reg: cfg_dedicated_io_13 */
  315. <0x00000134 0x000b282a>,
  316. /* Reg: cfg_dedicated_io_14 */
  317. <0x00000138 0x000b282a>,
  318. /* Reg: cfg_dedicated_io_15 */
  319. <0x0000013c 0x000b282a>,
  320. /* Reg: cfg_dedicated_io_16 */
  321. <0x00000140 0x0008282a>,
  322. /* Reg: cfg_dedicated_io_17 */
  323. <0x00000144 0x000a282a>;
  324. };
  325. /*
  326. * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
  327. * i_io48_pin_mux_fpga_interface_grp
  328. */
  329. fpga {
  330. u-boot,dm-pre-reloc;
  331. reg = <0xffd07400 0x00000100>;
  332. pinctrl-single,register-width = <32>;
  333. pinctrl-single,function-mask = <0x00000001>;
  334. pinctrl-single,pins =
  335. /* Reg: pinmux_emac0_usefpga */
  336. <0x00000000 0x00000000>,
  337. /* Reg: pinmux_emac1_usefpga */
  338. <0x00000004 0x00000000>,
  339. /* Reg: pinmux_emac2_usefpga */
  340. <0x00000008 0x00000000>,
  341. /* Reg: pinmux_i2c0_usefpga */
  342. <0x0000000c 0x00000000>,
  343. /* Reg: pinmux_i2c1_usefpga */
  344. <0x00000010 0x00000000>,
  345. /* Reg: pinmux_i2c_emac0_usefpga */
  346. <0x00000014 0x00000000>,
  347. /* Reg: pinmux_i2c_emac1_usefpga */
  348. <0x00000018 0x00000000>,
  349. /* Reg: pinmux_i2c_emac2_usefpga */
  350. <0x0000001c 0x00000000>,
  351. /* Reg: pinmux_nand_usefpga */
  352. <0x00000020 0x00000000>,
  353. /* Reg: pinmux_qspi_usefpga */
  354. <0x00000024 0x00000000>,
  355. /* Reg: pinmux_sdmmc_usefpga */
  356. <0x00000028 0x00000000>,
  357. /* Reg: pinmux_spim0_usefpga */
  358. <0x0000002c 0x00000000>,
  359. /* Reg: pinmux_spim1_usefpga */
  360. <0x00000030 0x00000000>,
  361. /* Reg: pinmux_spis0_usefpga */
  362. <0x00000034 0x00000000>,
  363. /* Reg: pinmux_spis1_usefpga */
  364. <0x00000038 0x00000000>,
  365. /* Reg: pinmux_uart0_usefpga */
  366. <0x0000003c 0x00000000>,
  367. /* Reg: pinmux_uart1_usefpga */
  368. <0x00000040 0x00000000>;
  369. };
  370. };
  371. i_noc: noc@0xffd10000 {
  372. u-boot,dm-pre-reloc;
  373. compatible = "altr,socfpga-a10-noc";
  374. reg = <0xffd10000 0x00008000>;
  375. reg-names = "mpu_m0";
  376. firewall {
  377. u-boot,dm-pre-reloc;
  378. /*
  379. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  380. * I_NOC.mpu_m0.
  381. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  382. * mpuregion0addr.base
  383. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  384. * I_NOC.mpu_m0.
  385. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  386. * mpuregion0addr.limit
  387. */
  388. altr,mpu0 = <0x00000000 0x0000ffff>;
  389. /*
  390. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  391. * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
  392. * hpsregion0addr.base
  393. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  394. * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
  395. * hpsregion0addr.limit
  396. */
  397. altr,l3-0 = <0x00000000 0x0000ffff>;
  398. /*
  399. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  400. * I_NOC.mpu_m0.
  401. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  402. * fpga2sdram0region0addr.base
  403. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  404. * I_NOC.mpu_m0.
  405. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  406. * fpga2sdram0region0addr.limit
  407. */
  408. altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
  409. /*
  410. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  411. * I_NOC.mpu_m0.
  412. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  413. * fpga2sdram1region0addr.base
  414. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  415. * I_NOC.mpu_m0.
  416. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  417. * fpga2sdram1region0addr.limit
  418. */
  419. altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
  420. /*
  421. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  422. * I_NOC.mpu_m0.
  423. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  424. * fpga2sdram2region0addr.base
  425. * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
  426. * I_NOC.mpu_m0.
  427. * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
  428. * fpga2sdram2region0addr.limit
  429. */
  430. altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
  431. };
  432. };
  433. hps_fpgabridge0: fpgabridge@0 {
  434. compatible = "altr,socfpga-hps2fpga-bridge";
  435. altr,init-val = <1>;
  436. };
  437. hps_fpgabridge1: fpgabridge@1 {
  438. compatible = "altr,socfpga-lwhps2fpga-bridge";
  439. altr,init-val = <1>;
  440. };
  441. hps_fpgabridge2: fpgabridge@2 {
  442. compatible = "altr,socfpga-fpga2hps-bridge";
  443. altr,init-val = <1>;
  444. };
  445. hps_fpgabridge3: fpgabridge@3 {
  446. compatible = "altr,socfpga-fpga2sdram0-bridge";
  447. altr,init-val = <1>;
  448. };
  449. hps_fpgabridge4: fpgabridge@4 {
  450. compatible = "altr,socfpga-fpga2sdram1-bridge";
  451. altr,init-val = <0>;
  452. };
  453. hps_fpgabridge5: fpgabridge@5 {
  454. compatible = "altr,socfpga-fpga2sdram2-bridge";
  455. altr,init-val = <1>;
  456. };
  457. };
  458. };