rk3xxx.dtsi 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright (c) 2013 MundoReader S.L.
  4. * Author: Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #include <dt-bindings/interrupt-controller/irq.h>
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include "skeleton.dtsi"
  9. / {
  10. interrupt-parent = <&gic>;
  11. aliases {
  12. ethernet0 = &emac;
  13. i2c0 = &i2c0;
  14. i2c1 = &i2c1;
  15. i2c2 = &i2c2;
  16. i2c3 = &i2c3;
  17. i2c4 = &i2c4;
  18. mshc0 = &emmc;
  19. mshc1 = &mmc0;
  20. mshc2 = &mmc1;
  21. serial0 = &uart0;
  22. serial1 = &uart1;
  23. serial2 = &uart2;
  24. serial3 = &uart3;
  25. spi0 = &spi0;
  26. spi1 = &spi1;
  27. };
  28. amba {
  29. compatible = "simple-bus";
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. ranges;
  33. dmac1_s: dma-controller@20018000 {
  34. compatible = "arm,pl330", "arm,primecell";
  35. reg = <0x20018000 0x4000>;
  36. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  37. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  38. #dma-cells = <1>;
  39. arm,pl330-broken-no-flushp;
  40. clocks = <&cru ACLK_DMA1>;
  41. clock-names = "apb_pclk";
  42. };
  43. dmac1_ns: dma-controller@2001c000 {
  44. compatible = "arm,pl330", "arm,primecell";
  45. reg = <0x2001c000 0x4000>;
  46. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  47. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  48. #dma-cells = <1>;
  49. arm,pl330-broken-no-flushp;
  50. clocks = <&cru ACLK_DMA1>;
  51. clock-names = "apb_pclk";
  52. status = "disabled";
  53. };
  54. dmac2: dma-controller@20078000 {
  55. compatible = "arm,pl330", "arm,primecell";
  56. reg = <0x20078000 0x4000>;
  57. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  58. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  59. #dma-cells = <1>;
  60. arm,pl330-broken-no-flushp;
  61. clocks = <&cru ACLK_DMA2>;
  62. clock-names = "apb_pclk";
  63. };
  64. };
  65. xin24m: oscillator {
  66. compatible = "fixed-clock";
  67. clock-frequency = <24000000>;
  68. #clock-cells = <0>;
  69. clock-output-names = "xin24m";
  70. };
  71. L2: l2-cache-controller@10138000 {
  72. compatible = "arm,pl310-cache";
  73. reg = <0x10138000 0x1000>;
  74. cache-unified;
  75. cache-level = <2>;
  76. };
  77. scu@1013c000 {
  78. compatible = "arm,cortex-a9-scu";
  79. reg = <0x1013c000 0x100>;
  80. };
  81. global_timer: global-timer@1013c200 {
  82. compatible = "arm,cortex-a9-global-timer";
  83. reg = <0x1013c200 0x20>;
  84. interrupts = <GIC_PPI 11 0x304>;
  85. clocks = <&cru CORE_PERI>;
  86. };
  87. local_timer: local-timer@1013c600 {
  88. compatible = "arm,cortex-a9-twd-timer";
  89. reg = <0x1013c600 0x20>;
  90. interrupts = <GIC_PPI 13 0x304>;
  91. clocks = <&cru CORE_PERI>;
  92. };
  93. gic: interrupt-controller@1013d000 {
  94. compatible = "arm,cortex-a9-gic";
  95. interrupt-controller;
  96. #interrupt-cells = <3>;
  97. reg = <0x1013d000 0x1000>,
  98. <0x1013c100 0x0100>;
  99. };
  100. uart0: serial@10124000 {
  101. compatible = "snps,dw-apb-uart";
  102. reg = <0x10124000 0x400>;
  103. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  104. reg-shift = <2>;
  105. reg-io-width = <1>;
  106. clock-names = "baudclk", "apb_pclk";
  107. clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  108. status = "disabled";
  109. };
  110. uart1: serial@10126000 {
  111. compatible = "snps,dw-apb-uart";
  112. reg = <0x10126000 0x400>;
  113. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  114. reg-shift = <2>;
  115. reg-io-width = <1>;
  116. clock-names = "baudclk", "apb_pclk";
  117. clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  118. status = "disabled";
  119. };
  120. noc: syscon@10128000 {
  121. u-boot,dm-spl;
  122. compatible = "rockchip,rk3188-noc", "syscon";
  123. reg = <0x10128000 0x2000>;
  124. };
  125. usb_otg: usb@10180000 {
  126. compatible = "rockchip,rk3066-usb", "snps,dwc2";
  127. reg = <0x10180000 0x40000>;
  128. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  129. clocks = <&cru HCLK_OTG0>;
  130. clock-names = "otg";
  131. dr_mode = "otg";
  132. g-np-tx-fifo-size = <16>;
  133. g-rx-fifo-size = <275>;
  134. g-tx-fifo-size = <256 128 128 64 64 32>;
  135. g-use-dma;
  136. phys = <&usbphy0>;
  137. phy-names = "usb2-phy";
  138. status = "disabled";
  139. };
  140. usb_host: usb@101c0000 {
  141. compatible = "snps,dwc2";
  142. reg = <0x101c0000 0x40000>;
  143. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  144. clocks = <&cru HCLK_OTG1>;
  145. clock-names = "otg";
  146. dr_mode = "host";
  147. phys = <&usbphy1>;
  148. phy-names = "usb2-phy";
  149. status = "disabled";
  150. };
  151. emac: ethernet@10204000 {
  152. compatible = "snps,arc-emac";
  153. reg = <0x10204000 0x3c>;
  154. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. rockchip,grf = <&grf>;
  158. clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
  159. clock-names = "hclk", "macref";
  160. max-speed = <100>;
  161. phy-mode = "rmii";
  162. status = "disabled";
  163. };
  164. mmc0: dwmmc@10214000 {
  165. compatible = "rockchip,rk2928-dw-mshc";
  166. reg = <0x10214000 0x1000>;
  167. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  168. clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
  169. clock-names = "biu", "ciu";
  170. fifo-depth = <256>;
  171. status = "disabled";
  172. };
  173. mmc1: dwmmc@10218000 {
  174. compatible = "rockchip,rk2928-dw-mshc";
  175. reg = <0x10218000 0x1000>;
  176. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  177. clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
  178. clock-names = "biu", "ciu";
  179. fifo-depth = <256>;
  180. status = "disabled";
  181. };
  182. emmc: dwmmc@1021c000 {
  183. compatible = "rockchip,rk2928-dw-mshc";
  184. reg = <0x1021c000 0x1000>;
  185. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  186. clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
  187. clock-names = "biu", "ciu";
  188. fifo-depth = <256>;
  189. status = "disabled";
  190. };
  191. pmu: pmu@20004000 {
  192. compatible = "rockchip,rk3066-pmu", "syscon";
  193. reg = <0x20004000 0x100>;
  194. u-boot,dm-spl;
  195. };
  196. grf: grf@20008000 {
  197. compatible = "syscon";
  198. reg = <0x20008000 0x200>;
  199. u-boot,dm-spl;
  200. };
  201. dmc: dmc@20020000 {
  202. /* unreviewed u-boot-specific binding */
  203. compatible = "rockchip,rk3188-dmc", "syscon";
  204. rockchip,cru = <&cru>;
  205. rockchip,grf = <&grf>;
  206. rockchip,pmu = <&pmu>;
  207. rockchip,noc = <&noc>;
  208. reg = <0x20020000 0x3fc
  209. 0x20040000 0x294>;
  210. clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;
  211. clock-names = "pclk_ddrupctl", "pclk_publ";
  212. u-boot,dm-spl;
  213. };
  214. i2c0: i2c@2002d000 {
  215. compatible = "rockchip,rk3066-i2c";
  216. reg = <0x2002d000 0x1000>;
  217. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. rockchip,grf = <&grf>;
  221. clock-names = "i2c";
  222. clocks = <&cru PCLK_I2C0>;
  223. status = "disabled";
  224. };
  225. i2c1: i2c@2002f000 {
  226. compatible = "rockchip,rk3066-i2c";
  227. reg = <0x2002f000 0x1000>;
  228. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  229. #address-cells = <1>;
  230. #size-cells = <0>;
  231. rockchip,grf = <&grf>;
  232. clocks = <&cru PCLK_I2C1>;
  233. clock-names = "i2c";
  234. status = "disabled";
  235. };
  236. pwm0: pwm@20030000 {
  237. compatible = "rockchip,rk2928-pwm";
  238. reg = <0x20030000 0x10>;
  239. #pwm-cells = <2>;
  240. clocks = <&cru PCLK_PWM01>;
  241. status = "disabled";
  242. };
  243. pwm1: pwm@20030010 {
  244. compatible = "rockchip,rk2928-pwm";
  245. reg = <0x20030010 0x10>;
  246. #pwm-cells = <2>;
  247. clocks = <&cru PCLK_PWM01>;
  248. status = "disabled";
  249. };
  250. wdt: watchdog@2004c000 {
  251. compatible = "snps,dw-wdt";
  252. reg = <0x2004c000 0x100>;
  253. clocks = <&cru PCLK_WDT>;
  254. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  255. status = "disabled";
  256. };
  257. pwm2: pwm@20050020 {
  258. compatible = "rockchip,rk2928-pwm";
  259. reg = <0x20050020 0x10>;
  260. #pwm-cells = <2>;
  261. clocks = <&cru PCLK_PWM23>;
  262. status = "disabled";
  263. };
  264. pwm3: pwm@20050030 {
  265. compatible = "rockchip,rk2928-pwm";
  266. reg = <0x20050030 0x10>;
  267. #pwm-cells = <2>;
  268. clocks = <&cru PCLK_PWM23>;
  269. status = "disabled";
  270. };
  271. i2c2: i2c@20056000 {
  272. compatible = "rockchip,rk3066-i2c";
  273. reg = <0x20056000 0x1000>;
  274. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. rockchip,grf = <&grf>;
  278. clocks = <&cru PCLK_I2C2>;
  279. clock-names = "i2c";
  280. status = "disabled";
  281. };
  282. i2c3: i2c@2005a000 {
  283. compatible = "rockchip,rk3066-i2c";
  284. reg = <0x2005a000 0x1000>;
  285. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. rockchip,grf = <&grf>;
  289. clocks = <&cru PCLK_I2C3>;
  290. clock-names = "i2c";
  291. status = "disabled";
  292. };
  293. i2c4: i2c@2005e000 {
  294. compatible = "rockchip,rk3066-i2c";
  295. reg = <0x2005e000 0x1000>;
  296. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. rockchip,grf = <&grf>;
  300. clocks = <&cru PCLK_I2C4>;
  301. clock-names = "i2c";
  302. status = "disabled";
  303. };
  304. uart2: serial@20064000 {
  305. compatible = "snps,dw-apb-uart";
  306. reg = <0x20064000 0x400>;
  307. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  308. reg-shift = <2>;
  309. reg-io-width = <1>;
  310. clock-frequency = <24000000>;
  311. clock-names = "baudclk", "apb_pclk";
  312. clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  313. status = "disabled";
  314. };
  315. uart3: serial@20068000 {
  316. compatible = "snps,dw-apb-uart";
  317. reg = <0x20068000 0x400>;
  318. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  319. reg-shift = <2>;
  320. reg-io-width = <1>;
  321. clock-names = "baudclk", "apb_pclk";
  322. clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
  323. status = "disabled";
  324. };
  325. saradc: saradc@2006c000 {
  326. compatible = "rockchip,saradc";
  327. reg = <0x2006c000 0x100>;
  328. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  329. #io-channel-cells = <1>;
  330. clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
  331. clock-names = "saradc", "apb_pclk";
  332. status = "disabled";
  333. };
  334. spi0: spi@20070000 {
  335. compatible = "rockchip,rk3066-spi";
  336. clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
  337. clock-names = "spiclk", "apb_pclk";
  338. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  339. reg = <0x20070000 0x1000>;
  340. #address-cells = <1>;
  341. #size-cells = <0>;
  342. dmas = <&dmac2 10>, <&dmac2 11>;
  343. dma-names = "tx", "rx";
  344. status = "disabled";
  345. };
  346. spi1: spi@20074000 {
  347. compatible = "rockchip,rk3066-spi";
  348. clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
  349. clock-names = "spiclk", "apb_pclk";
  350. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  351. reg = <0x20074000 0x1000>;
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354. dmas = <&dmac2 12>, <&dmac2 13>;
  355. dma-names = "tx", "rx";
  356. status = "disabled";
  357. };
  358. };