rk3368-lion-u-boot.dtsi 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  4. */
  5. / {
  6. config {
  7. u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
  8. u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
  9. };
  10. chosen {
  11. stdout-path = "serial0:115200n8";
  12. u-boot,spl-boot-order = &emmc, &sdmmc;
  13. tick-timer = "/timer@ff810000";
  14. };
  15. };
  16. &pinctrl {
  17. u-boot,dm-pre-reloc;
  18. };
  19. &service_msch {
  20. u-boot,dm-pre-reloc;
  21. };
  22. &dmc {
  23. u-boot,dm-pre-reloc;
  24. /*
  25. * Validation of throughput using SPEC2000 shows the following
  26. * relative performance for the different memory schedules:
  27. * - CBDR: 30.1
  28. * - CBRD: 29.8
  29. * - CRBD: 29.9
  30. * Note that the best performance for any given application workload
  31. * may vary from the default configured here (e.g. 164.gzip is fastest
  32. * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
  33. *
  34. * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
  35. * details on the 'rockchip,memory-schedule' property and how it
  36. * affects the physical-address to device-address mapping.
  37. */
  38. rockchip,memory-schedule = <DMC_MSCH_CBDR>;
  39. rockchip,ddr-frequency = <800000000>;
  40. rockchip,ddr-speed-bin = <DDR3_1600K>;
  41. status = "okay";
  42. };
  43. &pmugrf {
  44. u-boot,dm-pre-reloc;
  45. };
  46. &sgrf {
  47. u-boot,dm-pre-reloc;
  48. };
  49. &cru {
  50. u-boot,dm-pre-reloc;
  51. };
  52. &grf {
  53. u-boot,dm-pre-reloc;
  54. };
  55. &uart0 {
  56. u-boot,dm-pre-reloc;
  57. };
  58. &emmc {
  59. u-boot,dm-spl;
  60. };
  61. &sdmmc {
  62. u-boot,dm-spl;
  63. };
  64. &spi1 {
  65. u-boot,dm-spl;
  66. spiflash: w25q32dw@0 {
  67. u-boot,dm-spl;
  68. };
  69. };
  70. &timer0 {
  71. u-boot,dm-pre-reloc;
  72. clock-frequency = <24000000>;
  73. status = "okay";
  74. };