rk3188.dtsi 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright (c) 2013 MundoReader S.L.
  4. * Author: Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/pinctrl/rockchip.h>
  8. #include <dt-bindings/clock/rk3188-cru.h>
  9. #include "rk3xxx.dtsi"
  10. / {
  11. compatible = "rockchip,rk3188";
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. enable-method = "rockchip,rk3066-smp";
  16. cpu0: cpu@0 {
  17. device_type = "cpu";
  18. compatible = "arm,cortex-a9";
  19. next-level-cache = <&L2>;
  20. reg = <0x0>;
  21. operating-points = <
  22. /* kHz uV */
  23. 1608000 1350000
  24. 1416000 1250000
  25. 1200000 1150000
  26. 1008000 1075000
  27. 816000 975000
  28. 600000 950000
  29. 504000 925000
  30. 312000 875000
  31. >;
  32. clock-latency = <40000>;
  33. clocks = <&cru ARMCLK>;
  34. };
  35. cpu@1 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a9";
  38. next-level-cache = <&L2>;
  39. reg = <0x1>;
  40. };
  41. cpu@2 {
  42. device_type = "cpu";
  43. compatible = "arm,cortex-a9";
  44. next-level-cache = <&L2>;
  45. reg = <0x2>;
  46. };
  47. cpu@3 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a9";
  50. next-level-cache = <&L2>;
  51. reg = <0x3>;
  52. };
  53. };
  54. sram: sram@10080000 {
  55. compatible = "mmio-sram";
  56. reg = <0x10080000 0x8000>;
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. ranges = <0 0x10080000 0x8000>;
  60. smp-sram@0 {
  61. compatible = "rockchip,rk3066-smp-sram";
  62. reg = <0x0 0x50>;
  63. };
  64. };
  65. i2s0: i2s@1011a000 {
  66. compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
  67. reg = <0x1011a000 0x2000>;
  68. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&i2s0_bus>;
  73. dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  74. dma-names = "tx", "rx";
  75. clock-names = "i2s_hclk", "i2s_clk";
  76. clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  77. rockchip,playback-channels = <2>;
  78. rockchip,capture-channels = <2>;
  79. status = "disabled";
  80. };
  81. spdif: sound@1011e000 {
  82. compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
  83. reg = <0x1011e000 0x2000>;
  84. #sound-dai-cells = <0>;
  85. clock-names = "hclk", "mclk";
  86. clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
  87. dmas = <&dmac1_s 8>;
  88. dma-names = "tx";
  89. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&spdif_tx>;
  92. status = "disabled";
  93. };
  94. cru: clock-controller@20000000 {
  95. compatible = "rockchip,rk3188-cru";
  96. reg = <0x20000000 0x1000>;
  97. rockchip,grf = <&grf>;
  98. #clock-cells = <1>;
  99. #reset-cells = <1>;
  100. };
  101. efuse: efuse@20010000 {
  102. compatible = "rockchip,rockchip-efuse";
  103. reg = <0x20010000 0x4000>;
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. clocks = <&cru PCLK_EFUSE>;
  107. clock-names = "pclk_efuse";
  108. cpu_leakage: cpu_leakage@17 {
  109. reg = <0x17 0x1>;
  110. };
  111. };
  112. timer3: timer@2000e000 {
  113. compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
  114. reg = <0x2000e000 0x20>;
  115. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  116. };
  117. usbphy: phy {
  118. compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
  119. rockchip,grf = <&grf>;
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. status = "disabled";
  123. usbphy0: usb-phy@10c {
  124. #phy-cells = <0>;
  125. reg = <0x10c>;
  126. clocks = <&cru SCLK_OTGPHY0>;
  127. clock-names = "phyclk";
  128. #clock-cells = <0>;
  129. };
  130. usbphy1: usb-phy@11c {
  131. #phy-cells = <0>;
  132. reg = <0x11c>;
  133. clocks = <&cru SCLK_OTGPHY1>;
  134. clock-names = "phyclk";
  135. #clock-cells = <0>;
  136. };
  137. };
  138. pinctrl: pinctrl {
  139. compatible = "rockchip,rk3188-pinctrl";
  140. rockchip,grf = <&grf>;
  141. rockchip,pmu = <&pmu>;
  142. #address-cells = <1>;
  143. #size-cells = <1>;
  144. ranges;
  145. gpio0: gpio0@2000a000 {
  146. compatible = "rockchip,gpio-bank";
  147. reg = <0x2000a000 0x100>;
  148. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  149. clocks = <&cru PCLK_GPIO0>;
  150. gpio-controller;
  151. #gpio-cells = <2>;
  152. interrupt-controller;
  153. #interrupt-cells = <2>;
  154. };
  155. gpio1: gpio1@2003c000 {
  156. compatible = "rockchip,gpio-bank";
  157. reg = <0x2003c000 0x100>;
  158. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  159. clocks = <&cru PCLK_GPIO1>;
  160. gpio-controller;
  161. #gpio-cells = <2>;
  162. interrupt-controller;
  163. #interrupt-cells = <2>;
  164. };
  165. gpio2: gpio2@2003e000 {
  166. compatible = "rockchip,gpio-bank";
  167. reg = <0x2003e000 0x100>;
  168. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  169. clocks = <&cru PCLK_GPIO2>;
  170. gpio-controller;
  171. #gpio-cells = <2>;
  172. interrupt-controller;
  173. #interrupt-cells = <2>;
  174. };
  175. gpio3: gpio3@20080000 {
  176. compatible = "rockchip,gpio-bank";
  177. reg = <0x20080000 0x100>;
  178. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  179. clocks = <&cru PCLK_GPIO3>;
  180. gpio-controller;
  181. #gpio-cells = <2>;
  182. interrupt-controller;
  183. #interrupt-cells = <2>;
  184. };
  185. pcfg_pull_up: pcfg_pull_up {
  186. bias-pull-up;
  187. };
  188. pcfg_pull_down: pcfg_pull_down {
  189. bias-pull-down;
  190. };
  191. pcfg_pull_none: pcfg_pull_none {
  192. bias-disable;
  193. };
  194. emmc {
  195. emmc_clk: emmc-clk {
  196. rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
  197. };
  198. emmc_cmd: emmc-cmd {
  199. rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
  200. };
  201. emmc_rst: emmc-rst {
  202. rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
  203. };
  204. /*
  205. * The data pins are shared between nandc and emmc and
  206. * not accessible through pinctrl. Also they should've
  207. * been already set correctly by firmware, as
  208. * flash/emmc is the boot-device.
  209. */
  210. };
  211. emac {
  212. emac_xfer: emac-xfer {
  213. rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
  214. <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
  215. <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
  216. <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
  217. <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
  218. <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
  219. <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
  220. <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
  221. };
  222. emac_mdio: emac-mdio {
  223. rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
  224. <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
  225. };
  226. };
  227. i2c0 {
  228. i2c0_xfer: i2c0-xfer {
  229. rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
  230. <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
  231. };
  232. };
  233. i2c1 {
  234. i2c1_xfer: i2c1-xfer {
  235. rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
  236. <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
  237. };
  238. };
  239. i2c2 {
  240. i2c2_xfer: i2c2-xfer {
  241. rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
  242. <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
  243. };
  244. };
  245. i2c3 {
  246. i2c3_xfer: i2c3-xfer {
  247. rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
  248. <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
  249. };
  250. };
  251. i2c4 {
  252. i2c4_xfer: i2c4-xfer {
  253. rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
  254. <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
  255. };
  256. };
  257. pwm0 {
  258. pwm0_out: pwm0-out {
  259. rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
  260. };
  261. };
  262. pwm1 {
  263. pwm1_out: pwm1-out {
  264. rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
  265. };
  266. };
  267. pwm2 {
  268. pwm2_out: pwm2-out {
  269. rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
  270. };
  271. };
  272. pwm3 {
  273. pwm3_out: pwm3-out {
  274. rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
  275. };
  276. };
  277. spi0 {
  278. spi0_clk: spi0-clk {
  279. rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
  280. };
  281. spi0_cs0: spi0-cs0 {
  282. rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
  283. };
  284. spi0_tx: spi0-tx {
  285. rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
  286. };
  287. spi0_rx: spi0-rx {
  288. rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
  289. };
  290. spi0_cs1: spi0-cs1 {
  291. rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
  292. };
  293. };
  294. spi1 {
  295. spi1_clk: spi1-clk {
  296. rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
  297. };
  298. spi1_cs0: spi1-cs0 {
  299. rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
  300. };
  301. spi1_rx: spi1-rx {
  302. rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
  303. };
  304. spi1_tx: spi1-tx {
  305. rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
  306. };
  307. spi1_cs1: spi1-cs1 {
  308. rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
  309. };
  310. };
  311. uart0 {
  312. uart0_xfer: uart0-xfer {
  313. rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
  314. <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
  315. };
  316. uart0_cts: uart0-cts {
  317. rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
  318. };
  319. uart0_rts: uart0-rts {
  320. rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
  321. };
  322. };
  323. uart1 {
  324. uart1_xfer: uart1-xfer {
  325. rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
  326. <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
  327. };
  328. uart1_cts: uart1-cts {
  329. rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
  330. };
  331. uart1_rts: uart1-rts {
  332. rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
  333. };
  334. };
  335. uart2 {
  336. uart2_xfer: uart2-xfer {
  337. rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
  338. <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
  339. };
  340. /* no rts / cts for uart2 */
  341. };
  342. uart3 {
  343. uart3_xfer: uart3-xfer {
  344. rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
  345. <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
  346. };
  347. uart3_cts: uart3-cts {
  348. rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
  349. };
  350. uart3_rts: uart3-rts {
  351. rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
  352. };
  353. };
  354. sd0 {
  355. sd0_clk: sd0-clk {
  356. rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
  357. };
  358. sd0_cmd: sd0-cmd {
  359. rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
  360. };
  361. sd0_cd: sd0-cd {
  362. rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
  363. };
  364. sd0_wp: sd0-wp {
  365. rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
  366. };
  367. sd0_pwr: sd0-pwr {
  368. rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
  369. };
  370. sd0_bus1: sd0-bus-width1 {
  371. rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
  372. };
  373. sd0_bus4: sd0-bus-width4 {
  374. rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
  375. <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
  376. <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
  377. <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
  378. };
  379. };
  380. sd1 {
  381. sd1_clk: sd1-clk {
  382. rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
  383. };
  384. sd1_cmd: sd1-cmd {
  385. rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
  386. };
  387. sd1_cd: sd1-cd {
  388. rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
  389. };
  390. sd1_wp: sd1-wp {
  391. rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
  392. };
  393. sd1_bus1: sd1-bus-width1 {
  394. rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
  395. };
  396. sd1_bus4: sd1-bus-width4 {
  397. rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
  398. <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
  399. <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
  400. <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
  401. };
  402. };
  403. i2s0 {
  404. i2s0_bus: i2s0-bus {
  405. rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
  406. <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
  407. <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
  408. <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
  409. <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
  410. <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
  411. };
  412. };
  413. spdif {
  414. spdif_tx: spdif-tx {
  415. rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
  416. };
  417. };
  418. };
  419. };
  420. &emac {
  421. compatible = "rockchip,rk3188-emac";
  422. };
  423. &global_timer {
  424. interrupts = <GIC_PPI 11 0xf04>;
  425. };
  426. &grf {
  427. compatible = "rockchip,rk3188-grf", "syscon";
  428. };
  429. &local_timer {
  430. interrupts = <GIC_PPI 13 0xf04>;
  431. };
  432. &i2c0 {
  433. compatible = "rockchip,rk3188-i2c";
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&i2c0_xfer>;
  436. };
  437. &i2c1 {
  438. compatible = "rockchip,rk3188-i2c";
  439. pinctrl-names = "default";
  440. pinctrl-0 = <&i2c1_xfer>;
  441. };
  442. &i2c2 {
  443. compatible = "rockchip,rk3188-i2c";
  444. pinctrl-names = "default";
  445. pinctrl-0 = <&i2c2_xfer>;
  446. };
  447. &i2c3 {
  448. compatible = "rockchip,rk3188-i2c";
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&i2c3_xfer>;
  451. };
  452. &i2c4 {
  453. compatible = "rockchip,rk3188-i2c";
  454. pinctrl-names = "default";
  455. pinctrl-0 = <&i2c4_xfer>;
  456. };
  457. &pmu {
  458. compatible = "rockchip,rk3188-pmu", "syscon";
  459. };
  460. &pwm0 {
  461. pinctrl-names = "default";
  462. pinctrl-0 = <&pwm0_out>;
  463. };
  464. &pwm1 {
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pwm1_out>;
  467. };
  468. &pwm2 {
  469. pinctrl-names = "default";
  470. pinctrl-0 = <&pwm2_out>;
  471. };
  472. &pwm3 {
  473. pinctrl-names = "default";
  474. pinctrl-0 = <&pwm3_out>;
  475. };
  476. &spi0 {
  477. compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
  478. pinctrl-names = "default";
  479. pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  480. };
  481. &spi1 {
  482. compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
  483. pinctrl-names = "default";
  484. pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  485. };
  486. &uart0 {
  487. compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
  488. pinctrl-names = "default";
  489. pinctrl-0 = <&uart0_xfer>;
  490. };
  491. &uart1 {
  492. compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
  493. pinctrl-names = "default";
  494. pinctrl-0 = <&uart1_xfer>;
  495. };
  496. &uart2 {
  497. compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
  498. pinctrl-names = "default";
  499. pinctrl-0 = <&uart2_xfer>;
  500. };
  501. &uart3 {
  502. compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
  503. pinctrl-names = "default";
  504. pinctrl-0 = <&uart3_xfer>;
  505. };
  506. &wdt {
  507. compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
  508. };