meson-gxl-mali.dtsi 1.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 BayLibre SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. &apb {
  7. mali: gpu@c0000 {
  8. compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
  9. reg = <0x0 0xc0000 0x0 0x40000>;
  10. interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  11. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  12. <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  13. <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
  14. <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
  15. <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
  16. <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
  17. <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
  18. <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
  19. <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  20. interrupt-names = "gp", "gpmmu", "pp", "pmu",
  21. "pp0", "ppmmu0", "pp1", "ppmmu1",
  22. "pp2", "ppmmu2";
  23. clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
  24. clock-names = "bus", "core";
  25. /*
  26. * Mali clocking is provided by two identical clock paths
  27. * MALI_0 and MALI_1 muxed to a single clock by a glitch
  28. * free mux to safely change frequency while running.
  29. */
  30. assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
  31. <&clkc CLKID_MALI_0>,
  32. <&clkc CLKID_MALI>; /* Glitch free mux */
  33. assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  34. <0>, /* Do Nothing */
  35. <&clkc CLKID_MALI_0>;
  36. assigned-clock-rates = <0>, /* Do Nothing */
  37. <666666666>,
  38. <0>; /* Do Nothing */
  39. };
  40. };