fsl-ls2080a.dtsi 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Freescale ls2080a SOC common device tree source
  4. *
  5. * Copyright 2013-2015 Freescale Semiconductor, Inc.
  6. */
  7. / {
  8. compatible = "fsl,ls2080a";
  9. interrupt-parent = <&gic>;
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x00000000 0x80000000 0 0x80000000>;
  15. /* DRAM space - 1, size : 2 GB DRAM */
  16. };
  17. gic: interrupt-controller@6000000 {
  18. compatible = "arm,gic-v3";
  19. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  20. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. interrupts = <1 9 0x4>;
  24. };
  25. timer {
  26. compatible = "arm,armv8-timer";
  27. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  28. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  29. <1 11 0x8>, /* Virtual PPI, active-low */
  30. <1 10 0x8>; /* Hypervisor PPI, active-low */
  31. };
  32. serial0: serial@21c0500 {
  33. device_type = "serial";
  34. compatible = "fsl,ns16550", "ns16550a";
  35. reg = <0x0 0x21c0500 0x0 0x100>;
  36. clock-frequency = <0>; /* Updated by bootloader */
  37. interrupts = <0 32 0x1>; /* edge triggered */
  38. };
  39. serial1: serial@21c0600 {
  40. device_type = "serial";
  41. compatible = "fsl,ns16550", "ns16550a";
  42. reg = <0x0 0x21c0600 0x0 0x100>;
  43. clock-frequency = <0>; /* Updated by bootloader */
  44. interrupts = <0 32 0x1>; /* edge triggered */
  45. };
  46. fsl_mc: fsl-mc@80c000000 {
  47. compatible = "fsl,qoriq-mc";
  48. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  49. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  50. };
  51. dspi: dspi@2100000 {
  52. compatible = "fsl,vf610-dspi";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. reg = <0x0 0x2100000 0x0 0x10000>;
  56. interrupts = <0 26 0x4>; /* Level high type */
  57. num-cs = <6>;
  58. };
  59. qspi: quadspi@1550000 {
  60. compatible = "fsl,vf610-qspi";
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. reg = <0x0 0x20c0000 0x0 0x10000>,
  64. <0x0 0x20000000 0x0 0x10000000>;
  65. reg-names = "QuadSPI", "QuadSPI-memory";
  66. num-cs = <4>;
  67. };
  68. usb0: usb3@3100000 {
  69. compatible = "fsl,layerscape-dwc3";
  70. reg = <0x0 0x3100000 0x0 0x10000>;
  71. interrupts = <0 80 0x4>; /* Level high type */
  72. dr_mode = "host";
  73. };
  74. usb1: usb3@3110000 {
  75. compatible = "fsl,layerscape-dwc3";
  76. reg = <0x0 0x3110000 0x0 0x10000>;
  77. interrupts = <0 81 0x4>; /* Level high type */
  78. dr_mode = "host";
  79. };
  80. pcie@3400000 {
  81. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  82. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  83. 0x00 0x03480000 0x0 0x80000 /* lut registers */
  84. 0x10 0x00000000 0x0 0x20000>; /* configuration space */
  85. reg-names = "dbi", "lut", "config";
  86. #address-cells = <3>;
  87. #size-cells = <2>;
  88. device_type = "pci";
  89. num-lanes = <4>;
  90. bus-range = <0x0 0xff>;
  91. ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
  92. 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  93. };
  94. pcie@3500000 {
  95. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  96. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  97. 0x00 0x03580000 0x0 0x80000 /* lut registers */
  98. 0x12 0x00000000 0x0 0x20000>; /* configuration space */
  99. reg-names = "dbi", "lut", "config";
  100. #address-cells = <3>;
  101. #size-cells = <2>;
  102. device_type = "pci";
  103. num-lanes = <4>;
  104. bus-range = <0x0 0xff>;
  105. ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
  106. 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  107. };
  108. pcie@3600000 {
  109. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  110. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  111. 0x00 0x03680000 0x0 0x80000 /* lut registers */
  112. 0x14 0x00000000 0x0 0x20000>; /* configuration space */
  113. reg-names = "dbi", "lut", "config";
  114. #address-cells = <3>;
  115. #size-cells = <2>;
  116. device_type = "pci";
  117. num-lanes = <8>;
  118. bus-range = <0x0 0xff>;
  119. ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
  120. 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  121. };
  122. pcie@3700000 {
  123. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  124. reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
  125. 0x00 0x03780000 0x0 0x80000 /* lut registers */
  126. 0x16 0x00000000 0x0 0x20000>; /* configuration space */
  127. reg-names = "dbi", "lut", "config";
  128. #address-cells = <3>;
  129. #size-cells = <2>;
  130. device_type = "pci";
  131. num-lanes = <4>;
  132. bus-range = <0x0 0xff>;
  133. ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
  134. 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  135. };
  136. };