fsl-ls1088a.dtsi 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls1088a SOC common device tree source
  4. *
  5. * Copyright 2017 NXP
  6. */
  7. / {
  8. compatible = "fsl,ls1088a";
  9. interrupt-parent = <&gic>;
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x00000000 0x80000000 0 0x80000000>;
  15. /* DRAM space - 1, size : 2 GB DRAM */
  16. };
  17. gic: interrupt-controller@6000000 {
  18. compatible = "arm,gic-v3";
  19. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  20. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. interrupts = <1 9 0x4>;
  24. };
  25. timer {
  26. compatible = "arm,armv8-timer";
  27. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  28. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  29. <1 11 0x8>, /* Virtual PPI, active-low */
  30. <1 10 0x8>; /* Hypervisor PPI, active-low */
  31. };
  32. serial0: serial@21c0500 {
  33. device_type = "serial";
  34. compatible = "fsl,ns16550", "ns16550a";
  35. reg = <0x0 0x21c0500 0x0 0x100>;
  36. clock-frequency = <0>; /* Updated by bootloader */
  37. interrupts = <0 32 0x1>; /* edge triggered */
  38. };
  39. serial1: serial@21c0600 {
  40. device_type = "serial";
  41. compatible = "fsl,ns16550", "ns16550a";
  42. reg = <0x0 0x21c0600 0x0 0x100>;
  43. clock-frequency = <0>; /* Updated by bootloader */
  44. interrupts = <0 32 0x1>; /* edge triggered */
  45. };
  46. fsl_mc: fsl-mc@80c000000 {
  47. compatible = "fsl,qoriq-mc";
  48. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  49. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  50. };
  51. dspi: dspi@2100000 {
  52. compatible = "fsl,vf610-dspi";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. reg = <0x0 0x2100000 0x0 0x10000>;
  56. interrupts = <0 26 0x4>; /* Level high type */
  57. num-cs = <6>;
  58. };
  59. qspi: quadspi@1550000 {
  60. compatible = "fsl,vf610-qspi";
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. reg = <0x0 0x20c0000 0x0 0x10000>,
  64. <0x0 0x20000000 0x0 0x10000000>;
  65. reg-names = "QuadSPI", "QuadSPI-memory";
  66. num-cs = <4>;
  67. };
  68. ifc: ifc@1530000 {
  69. compatible = "fsl,ifc", "simple-bus";
  70. reg = <0x0 0x2240000 0x0 0x20000>;
  71. interrupts = <0 21 0x4>; /* Level high type */
  72. };
  73. usb0: usb3@3100000 {
  74. compatible = "fsl,layerscape-dwc3";
  75. reg = <0x0 0x3100000 0x0 0x10000>;
  76. interrupts = <0 80 0x4>; /* Level high type */
  77. dr_mode = "host";
  78. };
  79. usb1: usb3@3110000 {
  80. compatible = "fsl,layerscape-dwc3";
  81. reg = <0x0 0x3110000 0x0 0x10000>;
  82. interrupts = <0 81 0x4>; /* Level high type */
  83. dr_mode = "host";
  84. };
  85. pcie@3400000 {
  86. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  87. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  88. 0x00 0x03480000 0x0 0x80000 /* lut registers */
  89. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  90. 0x20 0x00000000 0x0 0x20000>; /* configuration space */
  91. reg-names = "dbi", "lut", "ctrl", "config";
  92. #address-cells = <3>;
  93. #size-cells = <2>;
  94. device_type = "pci";
  95. num-lanes = <4>;
  96. bus-range = <0x0 0xff>;
  97. ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
  98. 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  99. };
  100. pcie@3500000 {
  101. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  102. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  103. 0x00 0x03580000 0x0 0x80000 /* lut registers */
  104. 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
  105. 0x28 0x00000000 0x0 0x20000>; /* configuration space */
  106. reg-names = "dbi", "lut", "ctrl", "config";
  107. #address-cells = <3>;
  108. #size-cells = <2>;
  109. device_type = "pci";
  110. num-lanes = <4>;
  111. bus-range = <0x0 0xff>;
  112. ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
  113. 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  114. };
  115. pcie@3600000 {
  116. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  117. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  118. 0x00 0x03680000 0x0 0x80000 /* lut registers */
  119. 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
  120. 0x30 0x00000000 0x0 0x20000>; /* configuration space */
  121. reg-names = "dbi", "lut", "ctrl", "config";
  122. #address-cells = <3>;
  123. #size-cells = <2>;
  124. device_type = "pci";
  125. num-lanes = <8>;
  126. bus-range = <0x0 0xff>;
  127. ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
  128. 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  129. };
  130. };