fsl-ls1046a.dtsi 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  4. *
  5. * Copyright (C) 2016, Freescale Semiconductor
  6. *
  7. * Mingkai Hu <mingkai.hu@nxp.com>
  8. */
  9. /include/ "skeleton64.dtsi"
  10. / {
  11. compatible = "fsl,ls1046a";
  12. interrupt-parent = <&gic>;
  13. sysclk: sysclk {
  14. compatible = "fixed-clock";
  15. #clock-cells = <0>;
  16. clock-frequency = <100000000>;
  17. clock-output-names = "sysclk";
  18. };
  19. gic: interrupt-controller@1400000 {
  20. compatible = "arm,gic-400";
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. reg = <0x0 0x1410000 0 0x10000>, /* GICD */
  24. <0x0 0x1420000 0 0x10000>, /* GICC */
  25. <0x0 0x1440000 0 0x20000>, /* GICH */
  26. <0x0 0x1460000 0 0x20000>; /* GICV */
  27. interrupts = <1 9 0xf08>;
  28. };
  29. soc {
  30. compatible = "simple-bus";
  31. #address-cells = <2>;
  32. #size-cells = <2>;
  33. ranges;
  34. clockgen: clocking@1ee1000 {
  35. compatible = "fsl,ls1046a-clockgen";
  36. reg = <0x0 0x1ee1000 0x0 0x1000>;
  37. #clock-cells = <2>;
  38. clocks = <&sysclk>;
  39. };
  40. dspi0: dspi@2100000 {
  41. compatible = "fsl,vf610-dspi";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. reg = <0x0 0x2100000 0x0 0x10000>;
  45. interrupts = <0 64 0x4>;
  46. clock-names = "dspi";
  47. clocks = <&clockgen 4 0>;
  48. num-cs = <6>;
  49. big-endian;
  50. status = "disabled";
  51. };
  52. dspi1: dspi@2110000 {
  53. compatible = "fsl,vf610-dspi";
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. reg = <0x0 0x2110000 0x0 0x10000>;
  57. interrupts = <0 65 0x4>;
  58. clock-names = "dspi";
  59. clocks = <&clockgen 4 0>;
  60. num-cs = <6>;
  61. big-endian;
  62. status = "disabled";
  63. };
  64. ifc: ifc@1530000 {
  65. compatible = "fsl,ifc", "simple-bus";
  66. reg = <0x0 0x1530000 0x0 0x10000>;
  67. interrupts = <0 43 0x4>;
  68. };
  69. i2c0: i2c@2180000 {
  70. compatible = "fsl,vf610-i2c";
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. reg = <0x0 0x2180000 0x0 0x10000>;
  74. interrupts = <0 56 0x4>;
  75. clock-names = "i2c";
  76. clocks = <&clockgen 4 0>;
  77. status = "disabled";
  78. };
  79. i2c1: i2c@2190000 {
  80. compatible = "fsl,vf610-i2c";
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. reg = <0x0 0x2190000 0x0 0x10000>;
  84. interrupts = <0 57 0x4>;
  85. clock-names = "i2c";
  86. clocks = <&clockgen 4 0>;
  87. status = "disabled";
  88. };
  89. i2c2: i2c@21a0000 {
  90. compatible = "fsl,vf610-i2c";
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. reg = <0x0 0x21a0000 0x0 0x10000>;
  94. interrupts = <0 58 0x4>;
  95. clock-names = "i2c";
  96. clocks = <&clockgen 4 0>;
  97. status = "disabled";
  98. };
  99. i2c3: i2c@21b0000 {
  100. compatible = "fsl,vf610-i2c";
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. reg = <0x0 0x21b0000 0x0 0x10000>;
  104. interrupts = <0 59 0x4>;
  105. clock-names = "i2c";
  106. clocks = <&clockgen 4 0>;
  107. status = "disabled";
  108. };
  109. duart0: serial@21c0500 {
  110. compatible = "fsl,ns16550", "ns16550a";
  111. reg = <0x00 0x21c0500 0x0 0x100>;
  112. interrupts = <0 54 0x4>;
  113. clocks = <&clockgen 4 0>;
  114. };
  115. duart1: serial@21c0600 {
  116. compatible = "fsl,ns16550", "ns16550a";
  117. reg = <0x00 0x21c0600 0x0 0x100>;
  118. interrupts = <0 54 0x4>;
  119. clocks = <&clockgen 4 0>;
  120. };
  121. duart2: serial@21d0500 {
  122. compatible = "fsl,ns16550", "ns16550a";
  123. reg = <0x0 0x21d0500 0x0 0x100>;
  124. interrupts = <0 55 0x4>;
  125. clocks = <&clockgen 4 0>;
  126. };
  127. duart3: serial@21d0600 {
  128. compatible = "fsl,ns16550", "ns16550a";
  129. reg = <0x0 0x21d0600 0x0 0x100>;
  130. interrupts = <0 55 0x4>;
  131. clocks = <&clockgen 4 0>;
  132. };
  133. lpuart0: serial@2950000 {
  134. compatible = "fsl,ls1021a-lpuart";
  135. reg = <0x0 0x2950000 0x0 0x1000>;
  136. interrupts = <0 48 0x4>;
  137. clocks = <&clockgen 4 0>;
  138. clock-names = "ipg";
  139. status = "disabled";
  140. };
  141. lpuart1: serial@2960000 {
  142. compatible = "fsl,ls1021a-lpuart";
  143. reg = <0x0 0x2960000 0x0 0x1000>;
  144. interrupts = <0 49 0x4>;
  145. clocks = <&clockgen 4 1>;
  146. clock-names = "ipg";
  147. status = "disabled";
  148. };
  149. lpuart2: serial@2970000 {
  150. compatible = "fsl,ls1021a-lpuart";
  151. reg = <0x0 0x2970000 0x0 0x1000>;
  152. interrupts = <0 50 0x4>;
  153. clocks = <&clockgen 4 1>;
  154. clock-names = "ipg";
  155. status = "disabled";
  156. };
  157. lpuart3: serial@2980000 {
  158. compatible = "fsl,ls1021a-lpuart";
  159. reg = <0x0 0x2980000 0x0 0x1000>;
  160. interrupts = <0 51 0x4>;
  161. clocks = <&clockgen 4 1>;
  162. clock-names = "ipg";
  163. status = "disabled";
  164. };
  165. lpuart4: serial@2990000 {
  166. compatible = "fsl,ls1021a-lpuart";
  167. reg = <0x0 0x2990000 0x0 0x1000>;
  168. interrupts = <0 52 0x4>;
  169. clocks = <&clockgen 4 1>;
  170. clock-names = "ipg";
  171. status = "disabled";
  172. };
  173. lpuart5: serial@29a0000 {
  174. compatible = "fsl,ls1021a-lpuart";
  175. reg = <0x0 0x29a0000 0x0 0x1000>;
  176. interrupts = <0 53 0x4>;
  177. clocks = <&clockgen 4 1>;
  178. clock-names = "ipg";
  179. status = "disabled";
  180. };
  181. qspi: quadspi@1550000 {
  182. compatible = "fsl,vf610-qspi";
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. reg = <0x0 0x1550000 0x0 0x10000>,
  186. <0x0 0x40000000 0x0 0x10000000>;
  187. reg-names = "QuadSPI", "QuadSPI-memory";
  188. num-cs = <4>;
  189. big-endian;
  190. status = "disabled";
  191. };
  192. usb0: usb@2f00000 {
  193. compatible = "fsl,layerscape-dwc3";
  194. reg = <0x0 0x2f00000 0x0 0x10000>;
  195. interrupts = <0 60 4>;
  196. dr_mode = "host";
  197. };
  198. usb1: usb@3000000 {
  199. compatible = "fsl,layerscape-dwc3";
  200. reg = <0x0 0x3000000 0x0 0x10000>;
  201. interrupts = <0 61 4>;
  202. dr_mode = "host";
  203. };
  204. usb2: usb@3100000 {
  205. compatible = "fsl,layerscape-dwc3";
  206. reg = <0x0 0x3100000 0x0 0x10000>;
  207. interrupts = <0 63 4>;
  208. dr_mode = "host";
  209. };
  210. pcie@3400000 {
  211. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  212. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  213. 0x00 0x03480000 0x0 0x40000 /* lut registers */
  214. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  215. 0x40 0x00000000 0x0 0x20000>; /* configuration space */
  216. reg-names = "dbi", "lut", "ctrl", "config";
  217. big-endian;
  218. #address-cells = <3>;
  219. #size-cells = <2>;
  220. device_type = "pci";
  221. bus-range = <0x0 0xff>;
  222. ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
  223. 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  224. };
  225. pcie@3500000 {
  226. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  227. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  228. 0x00 0x03580000 0x0 0x40000 /* lut registers */
  229. 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
  230. 0x48 0x00000000 0x0 0x20000>; /* configuration space */
  231. reg-names = "dbi", "lut", "ctrl", "config";
  232. big-endian;
  233. #address-cells = <3>;
  234. #size-cells = <2>;
  235. device_type = "pci";
  236. num-lanes = <2>;
  237. bus-range = <0x0 0xff>;
  238. ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
  239. 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  240. };
  241. pcie@3600000 {
  242. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  243. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  244. 0x00 0x03680000 0x0 0x40000 /* lut registers */
  245. 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
  246. 0x50 0x00000000 0x0 0x20000>; /* configuration space */
  247. reg-names = "dbi", "lut", "ctrl", "config";
  248. big-endian;
  249. #address-cells = <3>;
  250. #size-cells = <2>;
  251. device_type = "pci";
  252. bus-range = <0x0 0xff>;
  253. ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
  254. 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  255. };
  256. };
  257. };