fsl-ls1043a-rdb.dts 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  4. *
  5. * Copyright (C) 2015, Freescale Semiconductor
  6. *
  7. * Mingkai Hu <Mingkai.hu@freescale.com>
  8. */
  9. /dts-v1/;
  10. /include/ "fsl-ls1043a.dtsi"
  11. / {
  12. model = "LS1043A RDB Board";
  13. aliases {
  14. spi1 = &dspi0;
  15. };
  16. };
  17. &dspi0 {
  18. bus-num = <0>;
  19. status = "okay";
  20. dspiflash: n25q12a {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "spi-flash";
  24. reg = <0>;
  25. spi-max-frequency = <1000000>; /* input clock */
  26. };
  27. };
  28. &i2c0 {
  29. status = "okay";
  30. ina220@40 {
  31. compatible = "ti,ina220";
  32. reg = <0x40>;
  33. shunt-resistor = <1000>;
  34. };
  35. adt7461a@4c {
  36. compatible = "adi,adt7461a";
  37. reg = <0x4c>;
  38. };
  39. eeprom@52 {
  40. compatible = "at24,24c512";
  41. reg = <0x52>;
  42. };
  43. eeprom@53 {
  44. compatible = "at24,24c512";
  45. reg = <0x53>;
  46. };
  47. rtc@68 {
  48. compatible = "pericom,pt7c4338";
  49. reg = <0x68>;
  50. };
  51. };
  52. &ifc {
  53. status = "okay";
  54. #address-cells = <2>;
  55. #size-cells = <1>;
  56. /* NOR, NAND Flashes and FPGA on board */
  57. ranges = <0x0 0x0 0x0 0x60000000 0x08000000
  58. 0x1 0x0 0x0 0x7e800000 0x00010000
  59. 0x2 0x0 0x0 0x7fb00000 0x00000100>;
  60. nor@0,0 {
  61. compatible = "cfi-flash";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0x0 0x0 0x8000000>;
  65. bank-width = <2>;
  66. device-width = <1>;
  67. };
  68. nand@1,0 {
  69. compatible = "fsl,ifc-nand";
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. reg = <0x1 0x0 0x10000>;
  73. };
  74. cpld: board-control@2,0 {
  75. compatible = "fsl,ls1043ardb-cpld";
  76. reg = <0x2 0x0 0x0000100>;
  77. };
  78. };
  79. &duart0 {
  80. status = "okay";
  81. };
  82. &duart1 {
  83. status = "okay";
  84. };