fsl-ls1043a-qds.dtsi 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  4. *
  5. * Copyright (C) 2015, Freescale Semiconductor
  6. *
  7. * Mingkai Hu <Mingkai.hu@freescale.com>
  8. */
  9. /include/ "fsl-ls1043a.dtsi"
  10. / {
  11. model = "LS1043A QDS Board";
  12. aliases {
  13. spi0 = &qspi;
  14. spi1 = &dspi0;
  15. };
  16. };
  17. &dspi0 {
  18. bus-num = <0>;
  19. status = "okay";
  20. dflash0: n25q128a {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "spi-flash";
  24. spi-max-frequency = <1000000>; /* input clock */
  25. spi-cpol;
  26. spi-cpha;
  27. reg = <0>;
  28. };
  29. dflash1: sst25wf040b {
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. compatible = "spi-flash";
  33. spi-max-frequency = <3500000>;
  34. spi-cpol;
  35. spi-cpha;
  36. reg = <1>;
  37. };
  38. dflash2: en25s64 {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. compatible = "spi-flash";
  42. spi-max-frequency = <3500000>;
  43. spi-cpol;
  44. spi-cpha;
  45. reg = <2>;
  46. };
  47. };
  48. &qspi {
  49. bus-num = <0>;
  50. status = "okay";
  51. qflash0: s25fl128s@0 {
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. compatible = "spi-flash";
  55. spi-max-frequency = <20000000>;
  56. reg = <0>;
  57. };
  58. };
  59. &i2c0 {
  60. status = "okay";
  61. pca9547@77 {
  62. compatible = "philips,pca9547";
  63. reg = <0x77>;
  64. #address-cells = <1>;
  65. #size-cells = <0>;
  66. i2c@0 {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69. reg = <0x0>;
  70. rtc@68 {
  71. compatible = "dallas,ds3232";
  72. reg = <0x68>;
  73. /* IRQ10_B */
  74. interrupts = <0 150 0x4>;
  75. };
  76. };
  77. i2c@2 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. reg = <0x2>;
  81. ina220@40 {
  82. compatible = "ti,ina220";
  83. reg = <0x40>;
  84. shunt-resistor = <1000>;
  85. };
  86. ina220@41 {
  87. compatible = "ti,ina220";
  88. reg = <0x41>;
  89. shunt-resistor = <1000>;
  90. };
  91. };
  92. i2c@3 {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. reg = <0x3>;
  96. eeprom@56 {
  97. compatible = "at24,24c512";
  98. reg = <0x56>;
  99. };
  100. eeprom@57 {
  101. compatible = "at24,24c512";
  102. reg = <0x57>;
  103. };
  104. adt7461a@4c {
  105. compatible = "adt7461a";
  106. reg = <0x4c>;
  107. };
  108. };
  109. };
  110. };
  111. &ifc {
  112. #address-cells = <2>;
  113. #size-cells = <1>;
  114. /* NOR, NAND Flashes and FPGA on board */
  115. ranges = <0x0 0x0 0x0 0x60000000 0x08000000
  116. 0x1 0x0 0x0 0x7e800000 0x00010000
  117. 0x2 0x0 0x0 0x7fb00000 0x00000100>;
  118. status = "okay";
  119. nor@0,0 {
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. compatible = "cfi-flash";
  123. reg = <0x0 0x0 0x8000000>;
  124. bank-width = <2>;
  125. device-width = <1>;
  126. };
  127. nand@1,0 {
  128. compatible = "fsl,ifc-nand";
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. reg = <0x1 0x0 0x10000>;
  132. };
  133. fpga: board-control@2,0 {
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. compatible = "simple-bus";
  137. reg = <0x2 0x0 0x0000100>;
  138. bank-width = <1>;
  139. device-width = <1>;
  140. ranges = <0 2 0 0x100>;
  141. };
  142. };
  143. &duart0 {
  144. status = "okay";
  145. };
  146. &duart1 {
  147. status = "okay";
  148. };
  149. &lpuart0 {
  150. status = "okay";
  151. };