fsl-ls1012a.dtsi 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152
  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. */
  5. /include/ "skeleton64.dtsi"
  6. / {
  7. compatible = "fsl,ls1012a";
  8. interrupt-parent = <&gic>;
  9. sysclk: sysclk {
  10. compatible = "fixed-clock";
  11. #clock-cells = <0>;
  12. clock-frequency = <100000000>;
  13. clock-output-names = "sysclk";
  14. };
  15. gic: interrupt-controller@1400000 {
  16. compatible = "arm,gic-400";
  17. #interrupt-cells = <3>;
  18. interrupt-controller;
  19. reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  20. <0x0 0x1402000 0 0x2000>, /* GICC */
  21. <0x0 0x1404000 0 0x2000>, /* GICH */
  22. <0x0 0x1406000 0 0x2000>; /* GICV */
  23. interrupts = <1 9 0xf08>;
  24. };
  25. soc {
  26. compatible = "simple-bus";
  27. #address-cells = <2>;
  28. #size-cells = <2>;
  29. ranges;
  30. clockgen: clocking@1ee1000 {
  31. compatible = "fsl,ls1012a-clockgen";
  32. reg = <0x0 0x1ee1000 0x0 0x1000>;
  33. #clock-cells = <2>;
  34. clocks = <&sysclk>;
  35. };
  36. dspi0: dspi@2100000 {
  37. compatible = "fsl,vf610-dspi";
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. reg = <0x0 0x2100000 0x0 0x10000>;
  41. interrupts = <0 64 0x4>;
  42. clock-names = "dspi";
  43. clocks = <&clockgen 4 0>;
  44. num-cs = <6>;
  45. big-endian;
  46. status = "disabled";
  47. };
  48. esdhc0: esdhc@1560000 {
  49. compatible = "fsl,esdhc";
  50. reg = <0x0 0x1560000 0x0 0x10000>;
  51. interrupts = <0 62 0x4>;
  52. big-endian;
  53. bus-width = <4>;
  54. };
  55. esdhc1: esdhc@1580000 {
  56. compatible = "fsl,esdhc";
  57. reg = <0x0 0x1580000 0x0 0x10000>;
  58. interrupts = <0 65 0x4>;
  59. big-endian;
  60. non-removable;
  61. bus-width = <4>;
  62. };
  63. i2c0: i2c@2180000 {
  64. compatible = "fsl,vf610-i2c";
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. reg = <0x0 0x2180000 0x0 0x10000>;
  68. interrupts = <0 56 0x4>;
  69. clock-names = "i2c";
  70. clocks = <&clockgen 4 0>;
  71. status = "disabled";
  72. };
  73. i2c1: i2c@2190000 {
  74. compatible = "fsl,vf610-i2c";
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. reg = <0x0 0x2190000 0x0 0x10000>;
  78. interrupts = <0 57 0x4>;
  79. clock-names = "i2c";
  80. clocks = <&clockgen 4 0>;
  81. status = "disabled";
  82. };
  83. duart0: serial@21c0500 {
  84. compatible = "fsl,ns16550", "ns16550a";
  85. reg = <0x00 0x21c0500 0x0 0x100>;
  86. interrupts = <0 54 0x4>;
  87. clocks = <&clockgen 4 0>;
  88. };
  89. duart1: serial@21c0600 {
  90. compatible = "fsl,ns16550", "ns16550a";
  91. reg = <0x00 0x21c0600 0x0 0x100>;
  92. interrupts = <0 54 0x4>;
  93. clocks = <&clockgen 4 0>;
  94. };
  95. qspi: quadspi@1550000 {
  96. compatible = "fsl,vf610-qspi";
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. reg = <0x0 0x1550000 0x0 0x10000>,
  100. <0x0 0x40000000 0x0 0x4000000>;
  101. reg-names = "QuadSPI", "QuadSPI-memory";
  102. num-cs = <1>;
  103. big-endian;
  104. status = "disabled";
  105. };
  106. pcie@3400000 {
  107. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  108. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  109. 0x00 0x03480000 0x0 0x40000 /* lut registers */
  110. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  111. 0x40 0x00000000 0x0 0x20000>; /* configuration space */
  112. reg-names = "dbi", "lut", "ctrl", "config";
  113. big-endian;
  114. #address-cells = <3>;
  115. #size-cells = <2>;
  116. device_type = "pci";
  117. bus-range = <0x0 0xff>;
  118. ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
  119. 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  120. };
  121. usb0: usb2@8600000 {
  122. compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
  123. reg = <0x0 0x8600000 0x0 0x1000>;
  124. interrupts = <0 139 0x4>;
  125. dr_mode = "host";
  126. fsl,usb-erratum-a005697;
  127. };
  128. usb1: usb3@2f00000 {
  129. compatible = "fsl,layerscape-dwc3";
  130. reg = <0x0 0x2f00000 0x0 0x10000>;
  131. interrupts = <0 61 0x4>;
  132. dr_mode = "host";
  133. };
  134. };
  135. };