pci_auto.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI autoconfiguration library
  4. *
  5. * Author: Matt Porter <mporter@mvista.com>
  6. *
  7. * Copyright 2000 MontaVista Software Inc.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <pci.h>
  13. /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  14. #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  15. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  16. #endif
  17. void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
  18. struct pci_region *mem,
  19. struct pci_region *prefetch, struct pci_region *io,
  20. bool enum_only)
  21. {
  22. u32 bar_response;
  23. pci_size_t bar_size;
  24. u16 cmdstat = 0;
  25. int bar, bar_nr = 0;
  26. u8 header_type;
  27. int rom_addr;
  28. pci_addr_t bar_value;
  29. struct pci_region *bar_res = NULL;
  30. int found_mem64 = 0;
  31. u16 class;
  32. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  33. cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
  34. PCI_COMMAND_MASTER;
  35. for (bar = PCI_BASE_ADDRESS_0;
  36. bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  37. /* Tickle the BAR and get the response */
  38. if (!enum_only)
  39. dm_pci_write_config32(dev, bar, 0xffffffff);
  40. dm_pci_read_config32(dev, bar, &bar_response);
  41. /* If BAR is not implemented go to the next BAR */
  42. if (!bar_response)
  43. continue;
  44. found_mem64 = 0;
  45. /* Check the BAR type and set our address mask */
  46. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  47. bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  48. & 0xffff) + 1;
  49. if (!enum_only)
  50. bar_res = io;
  51. debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  52. bar_nr, (unsigned long long)bar_size);
  53. } else {
  54. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  55. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  56. u32 bar_response_upper;
  57. u64 bar64;
  58. if (!enum_only) {
  59. dm_pci_write_config32(dev, bar + 4,
  60. 0xffffffff);
  61. }
  62. dm_pci_read_config32(dev, bar + 4,
  63. &bar_response_upper);
  64. bar64 = ((u64)bar_response_upper << 32) |
  65. bar_response;
  66. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
  67. + 1;
  68. if (!enum_only)
  69. found_mem64 = 1;
  70. } else {
  71. bar_size = (u32)(~(bar_response &
  72. PCI_BASE_ADDRESS_MEM_MASK) + 1);
  73. }
  74. if (!enum_only) {
  75. if (prefetch && (bar_response &
  76. PCI_BASE_ADDRESS_MEM_PREFETCH)) {
  77. bar_res = prefetch;
  78. } else {
  79. bar_res = mem;
  80. }
  81. }
  82. debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  83. bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  84. (unsigned long long)bar_size);
  85. }
  86. if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
  87. &bar_value,
  88. found_mem64) == 0) {
  89. /* Write it out and update our limit */
  90. dm_pci_write_config32(dev, bar, (u32)bar_value);
  91. if (found_mem64) {
  92. bar += 4;
  93. #ifdef CONFIG_SYS_PCI_64BIT
  94. dm_pci_write_config32(dev, bar,
  95. (u32)(bar_value >> 32));
  96. #else
  97. /*
  98. * If we are a 64-bit decoder then increment to
  99. * the upper 32 bits of the bar and force it to
  100. * locate in the lower 4GB of memory.
  101. */
  102. dm_pci_write_config32(dev, bar, 0x00000000);
  103. #endif
  104. }
  105. }
  106. cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
  107. PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
  108. debug("\n");
  109. bar_nr++;
  110. }
  111. if (!enum_only) {
  112. /* Configure the expansion ROM address */
  113. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  114. header_type &= 0x7f;
  115. if (header_type != PCI_HEADER_TYPE_CARDBUS) {
  116. rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
  117. PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
  118. dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
  119. dm_pci_read_config32(dev, rom_addr, &bar_response);
  120. if (bar_response) {
  121. bar_size = -(bar_response & ~1);
  122. debug("PCI Autoconfig: ROM, size=%#x, ",
  123. (unsigned int)bar_size);
  124. if (pciauto_region_allocate(mem, bar_size,
  125. &bar_value,
  126. false) == 0) {
  127. dm_pci_write_config32(dev, rom_addr,
  128. bar_value);
  129. }
  130. cmdstat |= PCI_COMMAND_MEMORY;
  131. debug("\n");
  132. }
  133. }
  134. }
  135. /* PCI_COMMAND_IO must be set for VGA device */
  136. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  137. if (class == PCI_CLASS_DISPLAY_VGA)
  138. cmdstat |= PCI_COMMAND_IO;
  139. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
  140. dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
  141. CONFIG_SYS_PCI_CACHE_LINE_SIZE);
  142. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
  143. }
  144. void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
  145. {
  146. struct pci_region *pci_mem;
  147. struct pci_region *pci_prefetch;
  148. struct pci_region *pci_io;
  149. u16 cmdstat, prefechable_64;
  150. struct udevice *ctlr = pci_get_controller(dev);
  151. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  152. pci_mem = ctlr_hose->pci_mem;
  153. pci_prefetch = ctlr_hose->pci_prefetch;
  154. pci_io = ctlr_hose->pci_io;
  155. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  156. dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
  157. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  158. /* Configure bus number registers */
  159. dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
  160. PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
  161. dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
  162. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
  163. if (pci_mem) {
  164. /* Round memory allocator to 1MB boundary */
  165. pciauto_region_align(pci_mem, 0x100000);
  166. /*
  167. * Set up memory and I/O filter limits, assume 32-bit
  168. * I/O space
  169. */
  170. dm_pci_write_config16(dev, PCI_MEMORY_BASE,
  171. (pci_mem->bus_lower & 0xfff00000) >> 16);
  172. cmdstat |= PCI_COMMAND_MEMORY;
  173. }
  174. if (pci_prefetch) {
  175. /* Round memory allocator to 1MB boundary */
  176. pciauto_region_align(pci_prefetch, 0x100000);
  177. /*
  178. * Set up memory and I/O filter limits, assume 32-bit
  179. * I/O space
  180. */
  181. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
  182. (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  183. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  184. #ifdef CONFIG_SYS_PCI_64BIT
  185. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
  186. pci_prefetch->bus_lower >> 32);
  187. #else
  188. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
  189. #endif
  190. cmdstat |= PCI_COMMAND_MEMORY;
  191. } else {
  192. /* We don't support prefetchable memory for now, so disable */
  193. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
  194. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  195. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  196. dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
  197. dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  198. }
  199. }
  200. if (pci_io) {
  201. /* Round I/O allocator to 4KB boundary */
  202. pciauto_region_align(pci_io, 0x1000);
  203. dm_pci_write_config8(dev, PCI_IO_BASE,
  204. (pci_io->bus_lower & 0x0000f000) >> 8);
  205. dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
  206. (pci_io->bus_lower & 0xffff0000) >> 16);
  207. cmdstat |= PCI_COMMAND_IO;
  208. }
  209. /* Enable memory and I/O accesses, enable bus master */
  210. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
  211. }
  212. void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
  213. {
  214. struct pci_region *pci_mem;
  215. struct pci_region *pci_prefetch;
  216. struct pci_region *pci_io;
  217. struct udevice *ctlr = pci_get_controller(dev);
  218. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  219. pci_mem = ctlr_hose->pci_mem;
  220. pci_prefetch = ctlr_hose->pci_prefetch;
  221. pci_io = ctlr_hose->pci_io;
  222. /* Configure bus number registers */
  223. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
  224. if (pci_mem) {
  225. /* Round memory allocator to 1MB boundary */
  226. pciauto_region_align(pci_mem, 0x100000);
  227. dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
  228. (pci_mem->bus_lower - 1) >> 16);
  229. }
  230. if (pci_prefetch) {
  231. u16 prefechable_64;
  232. dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
  233. &prefechable_64);
  234. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  235. /* Round memory allocator to 1MB boundary */
  236. pciauto_region_align(pci_prefetch, 0x100000);
  237. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
  238. (pci_prefetch->bus_lower - 1) >> 16);
  239. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  240. #ifdef CONFIG_SYS_PCI_64BIT
  241. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
  242. (pci_prefetch->bus_lower - 1) >> 32);
  243. #else
  244. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  245. #endif
  246. }
  247. if (pci_io) {
  248. /* Round I/O allocator to 4KB boundary */
  249. pciauto_region_align(pci_io, 0x1000);
  250. dm_pci_write_config8(dev, PCI_IO_LIMIT,
  251. ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
  252. dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
  253. ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
  254. }
  255. }
  256. /*
  257. * HJF: Changed this to return int. I think this is required
  258. * to get the correct result when scanning bridges
  259. */
  260. int dm_pciauto_config_device(struct udevice *dev)
  261. {
  262. struct pci_region *pci_mem;
  263. struct pci_region *pci_prefetch;
  264. struct pci_region *pci_io;
  265. unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
  266. unsigned short class;
  267. bool enum_only = false;
  268. struct udevice *ctlr = pci_get_controller(dev);
  269. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  270. int n;
  271. #ifdef CONFIG_PCI_ENUM_ONLY
  272. enum_only = true;
  273. #endif
  274. pci_mem = ctlr_hose->pci_mem;
  275. pci_prefetch = ctlr_hose->pci_prefetch;
  276. pci_io = ctlr_hose->pci_io;
  277. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  278. switch (class) {
  279. case PCI_CLASS_BRIDGE_PCI:
  280. debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  281. PCI_DEV(dm_pci_get_bdf(dev)));
  282. dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
  283. enum_only);
  284. n = dm_pci_hose_probe_bus(dev);
  285. if (n < 0)
  286. return n;
  287. sub_bus = (unsigned int)n;
  288. break;
  289. case PCI_CLASS_BRIDGE_CARDBUS:
  290. /*
  291. * just do a minimal setup of the bridge,
  292. * let the OS take care of the rest
  293. */
  294. dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
  295. enum_only);
  296. debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
  297. PCI_DEV(dm_pci_get_bdf(dev)));
  298. break;
  299. #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
  300. case PCI_CLASS_BRIDGE_OTHER:
  301. debug("PCI Autoconfig: Skipping bridge device %d\n",
  302. PCI_DEV(dm_pci_get_bdf(dev)));
  303. break;
  304. #endif
  305. #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
  306. !defined(CONFIG_TARGET_CADDY2)
  307. case PCI_CLASS_BRIDGE_OTHER:
  308. /*
  309. * The host/PCI bridge 1 seems broken in 8349 - it presents
  310. * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
  311. * device claiming resources io/mem/irq.. we only allow for
  312. * the PIMMR window to be allocated (BAR0 - 1MB size)
  313. */
  314. debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
  315. dm_pciauto_setup_device(dev, 0, hose->pci_mem,
  316. hose->pci_prefetch, hose->pci_io,
  317. enum_only);
  318. break;
  319. #endif
  320. case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
  321. debug("PCI AutoConfig: Found PowerPC device\n");
  322. /* fall through */
  323. default:
  324. dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
  325. enum_only);
  326. break;
  327. }
  328. return sub_bus;
  329. }