pci-uclass.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <dm/device-internal.h>
  12. #include <dm/lists.h>
  13. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  14. #include <asm/fsp/fsp_support.h>
  15. #endif
  16. #include "pci_internal.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int pci_get_bus(int busnum, struct udevice **busp)
  19. {
  20. int ret;
  21. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  22. /* Since buses may not be numbered yet try a little harder with bus 0 */
  23. if (ret == -ENODEV) {
  24. ret = uclass_first_device_err(UCLASS_PCI, busp);
  25. if (ret)
  26. return ret;
  27. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  28. }
  29. return ret;
  30. }
  31. struct udevice *pci_get_controller(struct udevice *dev)
  32. {
  33. while (device_is_on_pci_bus(dev))
  34. dev = dev->parent;
  35. return dev;
  36. }
  37. pci_dev_t dm_pci_get_bdf(struct udevice *dev)
  38. {
  39. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  40. struct udevice *bus = dev->parent;
  41. return PCI_ADD_BUS(bus->seq, pplat->devfn);
  42. }
  43. /**
  44. * pci_get_bus_max() - returns the bus number of the last active bus
  45. *
  46. * @return last bus number, or -1 if no active buses
  47. */
  48. static int pci_get_bus_max(void)
  49. {
  50. struct udevice *bus;
  51. struct uclass *uc;
  52. int ret = -1;
  53. ret = uclass_get(UCLASS_PCI, &uc);
  54. uclass_foreach_dev(bus, uc) {
  55. if (bus->seq > ret)
  56. ret = bus->seq;
  57. }
  58. debug("%s: ret=%d\n", __func__, ret);
  59. return ret;
  60. }
  61. int pci_last_busno(void)
  62. {
  63. return pci_get_bus_max();
  64. }
  65. int pci_get_ff(enum pci_size_t size)
  66. {
  67. switch (size) {
  68. case PCI_SIZE_8:
  69. return 0xff;
  70. case PCI_SIZE_16:
  71. return 0xffff;
  72. default:
  73. return 0xffffffff;
  74. }
  75. }
  76. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  77. ofnode *rnode)
  78. {
  79. struct fdt_pci_addr addr;
  80. ofnode node;
  81. int ret;
  82. dev_for_each_subnode(node, bus) {
  83. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  84. &addr);
  85. if (ret)
  86. continue;
  87. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  88. continue;
  89. *rnode = node;
  90. break;
  91. }
  92. };
  93. int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
  94. struct udevice **devp)
  95. {
  96. struct udevice *dev;
  97. for (device_find_first_child(bus, &dev);
  98. dev;
  99. device_find_next_child(&dev)) {
  100. struct pci_child_platdata *pplat;
  101. pplat = dev_get_parent_platdata(dev);
  102. if (pplat && pplat->devfn == find_devfn) {
  103. *devp = dev;
  104. return 0;
  105. }
  106. }
  107. return -ENODEV;
  108. }
  109. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  110. {
  111. struct udevice *bus;
  112. int ret;
  113. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  114. if (ret)
  115. return ret;
  116. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  117. }
  118. static int pci_device_matches_ids(struct udevice *dev,
  119. struct pci_device_id *ids)
  120. {
  121. struct pci_child_platdata *pplat;
  122. int i;
  123. pplat = dev_get_parent_platdata(dev);
  124. if (!pplat)
  125. return -EINVAL;
  126. for (i = 0; ids[i].vendor != 0; i++) {
  127. if (pplat->vendor == ids[i].vendor &&
  128. pplat->device == ids[i].device)
  129. return i;
  130. }
  131. return -EINVAL;
  132. }
  133. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  134. int *indexp, struct udevice **devp)
  135. {
  136. struct udevice *dev;
  137. /* Scan all devices on this bus */
  138. for (device_find_first_child(bus, &dev);
  139. dev;
  140. device_find_next_child(&dev)) {
  141. if (pci_device_matches_ids(dev, ids) >= 0) {
  142. if ((*indexp)-- <= 0) {
  143. *devp = dev;
  144. return 0;
  145. }
  146. }
  147. }
  148. return -ENODEV;
  149. }
  150. int pci_find_device_id(struct pci_device_id *ids, int index,
  151. struct udevice **devp)
  152. {
  153. struct udevice *bus;
  154. /* Scan all known buses */
  155. for (uclass_first_device(UCLASS_PCI, &bus);
  156. bus;
  157. uclass_next_device(&bus)) {
  158. if (!pci_bus_find_devices(bus, ids, &index, devp))
  159. return 0;
  160. }
  161. *devp = NULL;
  162. return -ENODEV;
  163. }
  164. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  165. unsigned int device, int *indexp,
  166. struct udevice **devp)
  167. {
  168. struct pci_child_platdata *pplat;
  169. struct udevice *dev;
  170. for (device_find_first_child(bus, &dev);
  171. dev;
  172. device_find_next_child(&dev)) {
  173. pplat = dev_get_parent_platdata(dev);
  174. if (pplat->vendor == vendor && pplat->device == device) {
  175. if (!(*indexp)--) {
  176. *devp = dev;
  177. return 0;
  178. }
  179. }
  180. }
  181. return -ENODEV;
  182. }
  183. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  184. struct udevice **devp)
  185. {
  186. struct udevice *bus;
  187. /* Scan all known buses */
  188. for (uclass_first_device(UCLASS_PCI, &bus);
  189. bus;
  190. uclass_next_device(&bus)) {
  191. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  192. return device_probe(*devp);
  193. }
  194. *devp = NULL;
  195. return -ENODEV;
  196. }
  197. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  198. {
  199. struct udevice *dev;
  200. /* Scan all known buses */
  201. for (pci_find_first_device(&dev);
  202. dev;
  203. pci_find_next_device(&dev)) {
  204. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  205. if (pplat->class == find_class && !index--) {
  206. *devp = dev;
  207. return device_probe(*devp);
  208. }
  209. }
  210. *devp = NULL;
  211. return -ENODEV;
  212. }
  213. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  214. unsigned long value, enum pci_size_t size)
  215. {
  216. struct dm_pci_ops *ops;
  217. ops = pci_get_ops(bus);
  218. if (!ops->write_config)
  219. return -ENOSYS;
  220. return ops->write_config(bus, bdf, offset, value, size);
  221. }
  222. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  223. u32 clr, u32 set)
  224. {
  225. ulong val;
  226. int ret;
  227. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  228. if (ret)
  229. return ret;
  230. val &= ~clr;
  231. val |= set;
  232. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  233. }
  234. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  235. enum pci_size_t size)
  236. {
  237. struct udevice *bus;
  238. int ret;
  239. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  240. if (ret)
  241. return ret;
  242. return pci_bus_write_config(bus, bdf, offset, value, size);
  243. }
  244. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  245. enum pci_size_t size)
  246. {
  247. struct udevice *bus;
  248. for (bus = dev; device_is_on_pci_bus(bus);)
  249. bus = bus->parent;
  250. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  251. size);
  252. }
  253. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  254. {
  255. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  256. }
  257. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  258. {
  259. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  260. }
  261. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  262. {
  263. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  264. }
  265. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  266. {
  267. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  268. }
  269. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  270. {
  271. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  272. }
  273. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  274. {
  275. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  276. }
  277. int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
  278. unsigned long *valuep, enum pci_size_t size)
  279. {
  280. struct dm_pci_ops *ops;
  281. ops = pci_get_ops(bus);
  282. if (!ops->read_config)
  283. return -ENOSYS;
  284. return ops->read_config(bus, bdf, offset, valuep, size);
  285. }
  286. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  287. enum pci_size_t size)
  288. {
  289. struct udevice *bus;
  290. int ret;
  291. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  292. if (ret)
  293. return ret;
  294. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  295. }
  296. int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
  297. enum pci_size_t size)
  298. {
  299. struct udevice *bus;
  300. for (bus = dev; device_is_on_pci_bus(bus);)
  301. bus = bus->parent;
  302. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  303. size);
  304. }
  305. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  306. {
  307. unsigned long value;
  308. int ret;
  309. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  310. if (ret)
  311. return ret;
  312. *valuep = value;
  313. return 0;
  314. }
  315. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  316. {
  317. unsigned long value;
  318. int ret;
  319. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  320. if (ret)
  321. return ret;
  322. *valuep = value;
  323. return 0;
  324. }
  325. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  326. {
  327. unsigned long value;
  328. int ret;
  329. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  330. if (ret)
  331. return ret;
  332. *valuep = value;
  333. return 0;
  334. }
  335. int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
  336. {
  337. unsigned long value;
  338. int ret;
  339. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  340. if (ret)
  341. return ret;
  342. *valuep = value;
  343. return 0;
  344. }
  345. int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
  346. {
  347. unsigned long value;
  348. int ret;
  349. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  350. if (ret)
  351. return ret;
  352. *valuep = value;
  353. return 0;
  354. }
  355. int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
  356. {
  357. unsigned long value;
  358. int ret;
  359. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  360. if (ret)
  361. return ret;
  362. *valuep = value;
  363. return 0;
  364. }
  365. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  366. {
  367. u8 val;
  368. int ret;
  369. ret = dm_pci_read_config8(dev, offset, &val);
  370. if (ret)
  371. return ret;
  372. val &= ~clr;
  373. val |= set;
  374. return dm_pci_write_config8(dev, offset, val);
  375. }
  376. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  377. {
  378. u16 val;
  379. int ret;
  380. ret = dm_pci_read_config16(dev, offset, &val);
  381. if (ret)
  382. return ret;
  383. val &= ~clr;
  384. val |= set;
  385. return dm_pci_write_config16(dev, offset, val);
  386. }
  387. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  388. {
  389. u32 val;
  390. int ret;
  391. ret = dm_pci_read_config32(dev, offset, &val);
  392. if (ret)
  393. return ret;
  394. val &= ~clr;
  395. val |= set;
  396. return dm_pci_write_config32(dev, offset, val);
  397. }
  398. static void set_vga_bridge_bits(struct udevice *dev)
  399. {
  400. struct udevice *parent = dev->parent;
  401. u16 bc;
  402. while (parent->seq != 0) {
  403. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  404. bc |= PCI_BRIDGE_CTL_VGA;
  405. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  406. parent = parent->parent;
  407. }
  408. }
  409. int pci_auto_config_devices(struct udevice *bus)
  410. {
  411. struct pci_controller *hose = bus->uclass_priv;
  412. struct pci_child_platdata *pplat;
  413. unsigned int sub_bus;
  414. struct udevice *dev;
  415. int ret;
  416. sub_bus = bus->seq;
  417. debug("%s: start\n", __func__);
  418. pciauto_config_init(hose);
  419. for (ret = device_find_first_child(bus, &dev);
  420. !ret && dev;
  421. ret = device_find_next_child(&dev)) {
  422. unsigned int max_bus;
  423. int ret;
  424. debug("%s: device %s\n", __func__, dev->name);
  425. ret = dm_pciauto_config_device(dev);
  426. if (ret < 0)
  427. return ret;
  428. max_bus = ret;
  429. sub_bus = max(sub_bus, max_bus);
  430. pplat = dev_get_parent_platdata(dev);
  431. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  432. set_vga_bridge_bits(dev);
  433. }
  434. debug("%s: done\n", __func__);
  435. return sub_bus;
  436. }
  437. int pci_generic_mmap_write_config(
  438. struct udevice *bus,
  439. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  440. pci_dev_t bdf,
  441. uint offset,
  442. ulong value,
  443. enum pci_size_t size)
  444. {
  445. void *address;
  446. if (addr_f(bus, bdf, offset, &address) < 0)
  447. return 0;
  448. switch (size) {
  449. case PCI_SIZE_8:
  450. writeb(value, address);
  451. return 0;
  452. case PCI_SIZE_16:
  453. writew(value, address);
  454. return 0;
  455. case PCI_SIZE_32:
  456. writel(value, address);
  457. return 0;
  458. default:
  459. return -EINVAL;
  460. }
  461. }
  462. int pci_generic_mmap_read_config(
  463. struct udevice *bus,
  464. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  465. pci_dev_t bdf,
  466. uint offset,
  467. ulong *valuep,
  468. enum pci_size_t size)
  469. {
  470. void *address;
  471. if (addr_f(bus, bdf, offset, &address) < 0) {
  472. *valuep = pci_get_ff(size);
  473. return 0;
  474. }
  475. switch (size) {
  476. case PCI_SIZE_8:
  477. *valuep = readb(address);
  478. return 0;
  479. case PCI_SIZE_16:
  480. *valuep = readw(address);
  481. return 0;
  482. case PCI_SIZE_32:
  483. *valuep = readl(address);
  484. return 0;
  485. default:
  486. return -EINVAL;
  487. }
  488. }
  489. int dm_pci_hose_probe_bus(struct udevice *bus)
  490. {
  491. int sub_bus;
  492. int ret;
  493. debug("%s\n", __func__);
  494. sub_bus = pci_get_bus_max() + 1;
  495. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  496. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  497. ret = device_probe(bus);
  498. if (ret) {
  499. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  500. ret);
  501. return ret;
  502. }
  503. if (sub_bus != bus->seq) {
  504. printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
  505. __func__, bus->name, bus->seq, sub_bus);
  506. return -EPIPE;
  507. }
  508. sub_bus = pci_get_bus_max();
  509. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  510. return sub_bus;
  511. }
  512. /**
  513. * pci_match_one_device - Tell if a PCI device structure has a matching
  514. * PCI device id structure
  515. * @id: single PCI device id structure to match
  516. * @find: the PCI device id structure to match against
  517. *
  518. * Returns true if the finding pci_device_id structure matched or false if
  519. * there is no match.
  520. */
  521. static bool pci_match_one_id(const struct pci_device_id *id,
  522. const struct pci_device_id *find)
  523. {
  524. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  525. (id->device == PCI_ANY_ID || id->device == find->device) &&
  526. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  527. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  528. !((id->class ^ find->class) & id->class_mask))
  529. return true;
  530. return false;
  531. }
  532. /**
  533. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  534. *
  535. * This only looks at certain fields in the descriptor.
  536. *
  537. * @parent: Parent bus
  538. * @find_id: Specification of the driver to find
  539. * @bdf: Bus/device/function addreess - see PCI_BDF()
  540. * @devp: Returns a pointer to the device created
  541. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  542. * therefore was not created, other -ve value on error
  543. */
  544. static int pci_find_and_bind_driver(struct udevice *parent,
  545. struct pci_device_id *find_id,
  546. pci_dev_t bdf, struct udevice **devp)
  547. {
  548. struct pci_driver_entry *start, *entry;
  549. ofnode node = ofnode_null();
  550. const char *drv;
  551. int n_ents;
  552. int ret;
  553. char name[30], *str;
  554. bool bridge;
  555. *devp = NULL;
  556. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  557. find_id->vendor, find_id->device);
  558. /* Determine optional OF node */
  559. pci_dev_find_ofnode(parent, bdf, &node);
  560. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  561. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  562. for (entry = start; entry != start + n_ents; entry++) {
  563. const struct pci_device_id *id;
  564. struct udevice *dev;
  565. const struct driver *drv;
  566. for (id = entry->match;
  567. id->vendor || id->subvendor || id->class_mask;
  568. id++) {
  569. if (!pci_match_one_id(id, find_id))
  570. continue;
  571. drv = entry->driver;
  572. /*
  573. * In the pre-relocation phase, we only bind devices
  574. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  575. * precious memory space as on some platforms as that
  576. * space is pretty limited (ie: using Cache As RAM).
  577. */
  578. if (!(gd->flags & GD_FLG_RELOC) &&
  579. !(drv->flags & DM_FLAG_PRE_RELOC))
  580. return -EPERM;
  581. /*
  582. * We could pass the descriptor to the driver as
  583. * platdata (instead of NULL) and allow its bind()
  584. * method to return -ENOENT if it doesn't support this
  585. * device. That way we could continue the search to
  586. * find another driver. For now this doesn't seem
  587. * necesssary, so just bind the first match.
  588. */
  589. ret = device_bind_ofnode(parent, drv, drv->name, NULL,
  590. node, &dev);
  591. if (ret)
  592. goto error;
  593. debug("%s: Match found: %s\n", __func__, drv->name);
  594. dev->driver_data = id->driver_data;
  595. *devp = dev;
  596. return 0;
  597. }
  598. }
  599. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  600. /*
  601. * In the pre-relocation phase, we only bind bridge devices to save
  602. * precious memory space as on some platforms as that space is pretty
  603. * limited (ie: using Cache As RAM).
  604. */
  605. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  606. return -EPERM;
  607. /* Bind a generic driver so that the device can be used */
  608. sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
  609. PCI_FUNC(bdf));
  610. str = strdup(name);
  611. if (!str)
  612. return -ENOMEM;
  613. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  614. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  615. if (ret) {
  616. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  617. free(str);
  618. return ret;
  619. }
  620. debug("%s: No match found: bound generic driver instead\n", __func__);
  621. return 0;
  622. error:
  623. debug("%s: No match found: error %d\n", __func__, ret);
  624. return ret;
  625. }
  626. int pci_bind_bus_devices(struct udevice *bus)
  627. {
  628. ulong vendor, device;
  629. ulong header_type;
  630. pci_dev_t bdf, end;
  631. bool found_multi;
  632. int ret;
  633. found_multi = false;
  634. end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
  635. PCI_MAX_PCI_FUNCTIONS - 1);
  636. for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
  637. bdf += PCI_BDF(0, 0, 1)) {
  638. struct pci_child_platdata *pplat;
  639. struct udevice *dev;
  640. ulong class;
  641. if (!PCI_FUNC(bdf))
  642. found_multi = false;
  643. if (PCI_FUNC(bdf) && !found_multi)
  644. continue;
  645. /* Check only the first access, we don't expect problems */
  646. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  647. PCI_SIZE_16);
  648. if (ret)
  649. goto error;
  650. if (vendor == 0xffff || vendor == 0x0000)
  651. continue;
  652. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  653. &header_type, PCI_SIZE_8);
  654. if (!PCI_FUNC(bdf))
  655. found_multi = header_type & 0x80;
  656. debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
  657. bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  658. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  659. PCI_SIZE_16);
  660. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  661. PCI_SIZE_32);
  662. class >>= 8;
  663. /* Find this device in the device tree */
  664. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  665. /* If nothing in the device tree, bind a device */
  666. if (ret == -ENODEV) {
  667. struct pci_device_id find_id;
  668. ulong val;
  669. memset(&find_id, '\0', sizeof(find_id));
  670. find_id.vendor = vendor;
  671. find_id.device = device;
  672. find_id.class = class;
  673. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  674. pci_bus_read_config(bus, bdf,
  675. PCI_SUBSYSTEM_VENDOR_ID,
  676. &val, PCI_SIZE_32);
  677. find_id.subvendor = val & 0xffff;
  678. find_id.subdevice = val >> 16;
  679. }
  680. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  681. &dev);
  682. }
  683. if (ret == -EPERM)
  684. continue;
  685. else if (ret)
  686. return ret;
  687. /* Update the platform data */
  688. pplat = dev_get_parent_platdata(dev);
  689. pplat->devfn = PCI_MASK_BUS(bdf);
  690. pplat->vendor = vendor;
  691. pplat->device = device;
  692. pplat->class = class;
  693. }
  694. return 0;
  695. error:
  696. printf("Cannot read bus configuration: %d\n", ret);
  697. return ret;
  698. }
  699. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  700. ofnode node)
  701. {
  702. int pci_addr_cells, addr_cells, size_cells;
  703. int cells_per_record;
  704. const u32 *prop;
  705. int len;
  706. int i;
  707. prop = ofnode_get_property(node, "ranges", &len);
  708. if (!prop) {
  709. debug("%s: Cannot decode regions\n", __func__);
  710. return;
  711. }
  712. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  713. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  714. size_cells = ofnode_read_simple_size_cells(node);
  715. /* PCI addresses are always 3-cells */
  716. len /= sizeof(u32);
  717. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  718. hose->region_count = 0;
  719. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  720. cells_per_record);
  721. for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
  722. u64 pci_addr, addr, size;
  723. int space_code;
  724. u32 flags;
  725. int type;
  726. int pos;
  727. if (len < cells_per_record)
  728. break;
  729. flags = fdt32_to_cpu(prop[0]);
  730. space_code = (flags >> 24) & 3;
  731. pci_addr = fdtdec_get_number(prop + 1, 2);
  732. prop += pci_addr_cells;
  733. addr = fdtdec_get_number(prop, addr_cells);
  734. prop += addr_cells;
  735. size = fdtdec_get_number(prop, size_cells);
  736. prop += size_cells;
  737. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  738. __func__, hose->region_count, pci_addr, addr, size, space_code);
  739. if (space_code & 2) {
  740. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  741. PCI_REGION_MEM;
  742. } else if (space_code & 1) {
  743. type = PCI_REGION_IO;
  744. } else {
  745. continue;
  746. }
  747. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  748. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  749. debug(" - beyond the 32-bit boundary, ignoring\n");
  750. continue;
  751. }
  752. pos = -1;
  753. for (i = 0; i < hose->region_count; i++) {
  754. if (hose->regions[i].flags == type)
  755. pos = i;
  756. }
  757. if (pos == -1)
  758. pos = hose->region_count++;
  759. debug(" - type=%d, pos=%d\n", type, pos);
  760. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  761. }
  762. /* Add a region for our local memory */
  763. #ifdef CONFIG_NR_DRAM_BANKS
  764. bd_t *bd = gd->bd;
  765. if (!bd)
  766. return;
  767. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  768. if (hose->region_count == MAX_PCI_REGIONS) {
  769. pr_err("maximum number of regions parsed, aborting\n");
  770. break;
  771. }
  772. if (bd->bi_dram[i].size) {
  773. pci_set_region(hose->regions + hose->region_count++,
  774. bd->bi_dram[i].start,
  775. bd->bi_dram[i].start,
  776. bd->bi_dram[i].size,
  777. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  778. }
  779. }
  780. #else
  781. phys_addr_t base = 0, size;
  782. size = gd->ram_size;
  783. #ifdef CONFIG_SYS_SDRAM_BASE
  784. base = CONFIG_SYS_SDRAM_BASE;
  785. #endif
  786. if (gd->pci_ram_top && gd->pci_ram_top < base + size)
  787. size = gd->pci_ram_top - base;
  788. if (size)
  789. pci_set_region(hose->regions + hose->region_count++, base,
  790. base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  791. #endif
  792. return;
  793. }
  794. static int pci_uclass_pre_probe(struct udevice *bus)
  795. {
  796. struct pci_controller *hose;
  797. debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
  798. bus->parent->name);
  799. hose = bus->uclass_priv;
  800. /* For bridges, use the top-level PCI controller */
  801. if (!device_is_on_pci_bus(bus)) {
  802. hose->ctlr = bus;
  803. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  804. } else {
  805. struct pci_controller *parent_hose;
  806. parent_hose = dev_get_uclass_priv(bus->parent);
  807. hose->ctlr = parent_hose->bus;
  808. }
  809. hose->bus = bus;
  810. hose->first_busno = bus->seq;
  811. hose->last_busno = bus->seq;
  812. return 0;
  813. }
  814. static int pci_uclass_post_probe(struct udevice *bus)
  815. {
  816. int ret;
  817. debug("%s: probing bus %d\n", __func__, bus->seq);
  818. ret = pci_bind_bus_devices(bus);
  819. if (ret)
  820. return ret;
  821. #ifdef CONFIG_PCI_PNP
  822. ret = pci_auto_config_devices(bus);
  823. if (ret < 0)
  824. return ret;
  825. #endif
  826. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  827. /*
  828. * Per Intel FSP specification, we should call FSP notify API to
  829. * inform FSP that PCI enumeration has been done so that FSP will
  830. * do any necessary initialization as required by the chipset's
  831. * BIOS Writer's Guide (BWG).
  832. *
  833. * Unfortunately we have to put this call here as with driver model,
  834. * the enumeration is all done on a lazy basis as needed, so until
  835. * something is touched on PCI it won't happen.
  836. *
  837. * Note we only call this 1) after U-Boot is relocated, and 2)
  838. * root bus has finished probing.
  839. */
  840. if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
  841. ret = fsp_init_phase_pci();
  842. if (ret)
  843. return ret;
  844. }
  845. #endif
  846. return 0;
  847. }
  848. int pci_get_devfn(struct udevice *dev)
  849. {
  850. struct fdt_pci_addr addr;
  851. int ret;
  852. /* Extract the devfn from fdt_pci_addr */
  853. ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG,
  854. "reg", &addr);
  855. if (ret) {
  856. if (ret != -ENOENT)
  857. return -EINVAL;
  858. }
  859. return addr.phys_hi & 0xff00;
  860. }
  861. static int pci_uclass_child_post_bind(struct udevice *dev)
  862. {
  863. struct pci_child_platdata *pplat;
  864. if (!dev_of_valid(dev))
  865. return 0;
  866. pplat = dev_get_parent_platdata(dev);
  867. /* Extract vendor id and device id if available */
  868. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  869. /* Extract the devfn from fdt_pci_addr */
  870. pplat->devfn = pci_get_devfn(dev);
  871. return 0;
  872. }
  873. static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
  874. uint offset, ulong *valuep,
  875. enum pci_size_t size)
  876. {
  877. struct pci_controller *hose = bus->uclass_priv;
  878. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  879. }
  880. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  881. uint offset, ulong value,
  882. enum pci_size_t size)
  883. {
  884. struct pci_controller *hose = bus->uclass_priv;
  885. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  886. }
  887. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  888. {
  889. struct udevice *dev;
  890. int ret = 0;
  891. /*
  892. * Scan through all the PCI controllers. On x86 there will only be one
  893. * but that is not necessarily true on other hardware.
  894. */
  895. do {
  896. device_find_first_child(bus, &dev);
  897. if (dev) {
  898. *devp = dev;
  899. return 0;
  900. }
  901. ret = uclass_next_device(&bus);
  902. if (ret)
  903. return ret;
  904. } while (bus);
  905. return 0;
  906. }
  907. int pci_find_next_device(struct udevice **devp)
  908. {
  909. struct udevice *child = *devp;
  910. struct udevice *bus = child->parent;
  911. int ret;
  912. /* First try all the siblings */
  913. *devp = NULL;
  914. while (child) {
  915. device_find_next_child(&child);
  916. if (child) {
  917. *devp = child;
  918. return 0;
  919. }
  920. }
  921. /* We ran out of siblings. Try the next bus */
  922. ret = uclass_next_device(&bus);
  923. if (ret)
  924. return ret;
  925. return bus ? skip_to_next_device(bus, devp) : 0;
  926. }
  927. int pci_find_first_device(struct udevice **devp)
  928. {
  929. struct udevice *bus;
  930. int ret;
  931. *devp = NULL;
  932. ret = uclass_first_device(UCLASS_PCI, &bus);
  933. if (ret)
  934. return ret;
  935. return skip_to_next_device(bus, devp);
  936. }
  937. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  938. {
  939. switch (size) {
  940. case PCI_SIZE_8:
  941. return (value >> ((offset & 3) * 8)) & 0xff;
  942. case PCI_SIZE_16:
  943. return (value >> ((offset & 2) * 8)) & 0xffff;
  944. default:
  945. return value;
  946. }
  947. }
  948. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  949. enum pci_size_t size)
  950. {
  951. uint off_mask;
  952. uint val_mask, shift;
  953. ulong ldata, mask;
  954. switch (size) {
  955. case PCI_SIZE_8:
  956. off_mask = 3;
  957. val_mask = 0xff;
  958. break;
  959. case PCI_SIZE_16:
  960. off_mask = 2;
  961. val_mask = 0xffff;
  962. break;
  963. default:
  964. return value;
  965. }
  966. shift = (offset & off_mask) * 8;
  967. ldata = (value & val_mask) << shift;
  968. mask = val_mask << shift;
  969. value = (old & ~mask) | ldata;
  970. return value;
  971. }
  972. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  973. struct pci_region **memp, struct pci_region **prefp)
  974. {
  975. struct udevice *bus = pci_get_controller(dev);
  976. struct pci_controller *hose = dev_get_uclass_priv(bus);
  977. int i;
  978. *iop = NULL;
  979. *memp = NULL;
  980. *prefp = NULL;
  981. for (i = 0; i < hose->region_count; i++) {
  982. switch (hose->regions[i].flags) {
  983. case PCI_REGION_IO:
  984. if (!*iop || (*iop)->size < hose->regions[i].size)
  985. *iop = hose->regions + i;
  986. break;
  987. case PCI_REGION_MEM:
  988. if (!*memp || (*memp)->size < hose->regions[i].size)
  989. *memp = hose->regions + i;
  990. break;
  991. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  992. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  993. *prefp = hose->regions + i;
  994. break;
  995. }
  996. }
  997. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  998. }
  999. u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
  1000. {
  1001. u32 addr;
  1002. int bar;
  1003. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1004. dm_pci_read_config32(dev, bar, &addr);
  1005. if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1006. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1007. else
  1008. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1009. }
  1010. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1011. {
  1012. int bar;
  1013. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1014. dm_pci_write_config32(dev, bar, addr);
  1015. }
  1016. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1017. pci_addr_t bus_addr, unsigned long flags,
  1018. unsigned long skip_mask, phys_addr_t *pa)
  1019. {
  1020. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1021. struct pci_region *res;
  1022. int i;
  1023. if (hose->region_count == 0) {
  1024. *pa = bus_addr;
  1025. return 0;
  1026. }
  1027. for (i = 0; i < hose->region_count; i++) {
  1028. res = &hose->regions[i];
  1029. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1030. continue;
  1031. if (res->flags & skip_mask)
  1032. continue;
  1033. if (bus_addr >= res->bus_start &&
  1034. (bus_addr - res->bus_start) < res->size) {
  1035. *pa = (bus_addr - res->bus_start + res->phys_start);
  1036. return 0;
  1037. }
  1038. }
  1039. return 1;
  1040. }
  1041. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1042. unsigned long flags)
  1043. {
  1044. phys_addr_t phys_addr = 0;
  1045. struct udevice *ctlr;
  1046. int ret;
  1047. /* The root controller has the region information */
  1048. ctlr = pci_get_controller(dev);
  1049. /*
  1050. * if PCI_REGION_MEM is set we do a two pass search with preference
  1051. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1052. */
  1053. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1054. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1055. flags, PCI_REGION_SYS_MEMORY,
  1056. &phys_addr);
  1057. if (!ret)
  1058. return phys_addr;
  1059. }
  1060. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1061. if (ret)
  1062. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1063. return phys_addr;
  1064. }
  1065. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1066. unsigned long flags, unsigned long skip_mask,
  1067. pci_addr_t *ba)
  1068. {
  1069. struct pci_region *res;
  1070. struct udevice *ctlr;
  1071. pci_addr_t bus_addr;
  1072. int i;
  1073. struct pci_controller *hose;
  1074. /* The root controller has the region information */
  1075. ctlr = pci_get_controller(dev);
  1076. hose = dev_get_uclass_priv(ctlr);
  1077. if (hose->region_count == 0) {
  1078. *ba = phys_addr;
  1079. return 0;
  1080. }
  1081. for (i = 0; i < hose->region_count; i++) {
  1082. res = &hose->regions[i];
  1083. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1084. continue;
  1085. if (res->flags & skip_mask)
  1086. continue;
  1087. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1088. if (bus_addr >= res->bus_start &&
  1089. (bus_addr - res->bus_start) < res->size) {
  1090. *ba = bus_addr;
  1091. return 0;
  1092. }
  1093. }
  1094. return 1;
  1095. }
  1096. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1097. unsigned long flags)
  1098. {
  1099. pci_addr_t bus_addr = 0;
  1100. int ret;
  1101. /*
  1102. * if PCI_REGION_MEM is set we do a two pass search with preference
  1103. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1104. */
  1105. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1106. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1107. PCI_REGION_SYS_MEMORY, &bus_addr);
  1108. if (!ret)
  1109. return bus_addr;
  1110. }
  1111. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1112. if (ret)
  1113. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1114. return bus_addr;
  1115. }
  1116. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1117. int ea_off)
  1118. {
  1119. int ea_cnt, i, entry_size;
  1120. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1121. u32 ea_entry;
  1122. phys_addr_t addr;
  1123. /* EA capability structure header */
  1124. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1125. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1126. ea_off += PCI_EA_FIRST_ENT;
  1127. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1128. /* Entry header */
  1129. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1130. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1131. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1132. continue;
  1133. /* Base address, 1st DW */
  1134. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1135. addr = ea_entry & PCI_EA_FIELD_MASK;
  1136. if (ea_entry & PCI_EA_IS_64) {
  1137. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1138. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1139. addr |= ((u64)ea_entry) << 32;
  1140. }
  1141. /* size ignored for now */
  1142. return map_physmem(addr, flags, 0);
  1143. }
  1144. return 0;
  1145. }
  1146. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1147. {
  1148. pci_addr_t pci_bus_addr;
  1149. u32 bar_response;
  1150. int ea_off;
  1151. /*
  1152. * if the function supports Enhanced Allocation use that instead of
  1153. * BARs
  1154. */
  1155. ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
  1156. if (ea_off)
  1157. return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
  1158. /* read BAR address */
  1159. dm_pci_read_config32(dev, bar, &bar_response);
  1160. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1161. /*
  1162. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1163. * isn't actualy used on any platform because u-boot assumes a static
  1164. * linear mapping. In the future, this could read the BAR size
  1165. * and pass that as the size if needed.
  1166. */
  1167. return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1168. }
  1169. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1170. {
  1171. int ttl = PCI_FIND_CAP_TTL;
  1172. u8 id;
  1173. u16 ent;
  1174. dm_pci_read_config8(dev, pos, &pos);
  1175. while (ttl--) {
  1176. if (pos < PCI_STD_HEADER_SIZEOF)
  1177. break;
  1178. pos &= ~3;
  1179. dm_pci_read_config16(dev, pos, &ent);
  1180. id = ent & 0xff;
  1181. if (id == 0xff)
  1182. break;
  1183. if (id == cap)
  1184. return pos;
  1185. pos = (ent >> 8);
  1186. }
  1187. return 0;
  1188. }
  1189. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1190. {
  1191. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1192. cap);
  1193. }
  1194. int dm_pci_find_capability(struct udevice *dev, int cap)
  1195. {
  1196. u16 status;
  1197. u8 header_type;
  1198. u8 pos;
  1199. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1200. if (!(status & PCI_STATUS_CAP_LIST))
  1201. return 0;
  1202. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1203. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1204. pos = PCI_CB_CAPABILITY_LIST;
  1205. else
  1206. pos = PCI_CAPABILITY_LIST;
  1207. return _dm_pci_find_next_capability(dev, pos, cap);
  1208. }
  1209. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1210. {
  1211. u32 header;
  1212. int ttl;
  1213. int pos = PCI_CFG_SPACE_SIZE;
  1214. /* minimum 8 bytes per capability */
  1215. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1216. if (start)
  1217. pos = start;
  1218. dm_pci_read_config32(dev, pos, &header);
  1219. /*
  1220. * If we have no capabilities, this is indicated by cap ID,
  1221. * cap version and next pointer all being 0.
  1222. */
  1223. if (header == 0)
  1224. return 0;
  1225. while (ttl--) {
  1226. if (PCI_EXT_CAP_ID(header) == cap)
  1227. return pos;
  1228. pos = PCI_EXT_CAP_NEXT(header);
  1229. if (pos < PCI_CFG_SPACE_SIZE)
  1230. break;
  1231. dm_pci_read_config32(dev, pos, &header);
  1232. }
  1233. return 0;
  1234. }
  1235. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1236. {
  1237. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1238. }
  1239. int dm_pci_flr(struct udevice *dev)
  1240. {
  1241. int pcie_off;
  1242. u32 cap;
  1243. /* look for PCI Express Capability */
  1244. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1245. if (!pcie_off)
  1246. return -ENOENT;
  1247. /* check FLR capability */
  1248. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1249. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1250. return -ENOENT;
  1251. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1252. PCI_EXP_DEVCTL_BCR_FLR);
  1253. /* wait 100ms, per PCI spec */
  1254. mdelay(100);
  1255. return 0;
  1256. }
  1257. UCLASS_DRIVER(pci) = {
  1258. .id = UCLASS_PCI,
  1259. .name = "pci",
  1260. .flags = DM_UC_FLAG_SEQ_ALIAS,
  1261. .post_bind = dm_scan_fdt_dev,
  1262. .pre_probe = pci_uclass_pre_probe,
  1263. .post_probe = pci_uclass_post_probe,
  1264. .child_post_bind = pci_uclass_child_post_bind,
  1265. .per_device_auto_alloc_size = sizeof(struct pci_controller),
  1266. .per_child_platdata_auto_alloc_size =
  1267. sizeof(struct pci_child_platdata),
  1268. };
  1269. static const struct dm_pci_ops pci_bridge_ops = {
  1270. .read_config = pci_bridge_read_config,
  1271. .write_config = pci_bridge_write_config,
  1272. };
  1273. static const struct udevice_id pci_bridge_ids[] = {
  1274. { .compatible = "pci-bridge" },
  1275. { }
  1276. };
  1277. U_BOOT_DRIVER(pci_bridge_drv) = {
  1278. .name = "pci_bridge_drv",
  1279. .id = UCLASS_PCI,
  1280. .of_match = pci_bridge_ids,
  1281. .ops = &pci_bridge_ops,
  1282. };
  1283. UCLASS_DRIVER(pci_generic) = {
  1284. .id = UCLASS_PCI_GENERIC,
  1285. .name = "pci_generic",
  1286. };
  1287. static const struct udevice_id pci_generic_ids[] = {
  1288. { .compatible = "pci-generic" },
  1289. { }
  1290. };
  1291. U_BOOT_DRIVER(pci_generic_drv) = {
  1292. .name = "pci_generic_drv",
  1293. .id = UCLASS_PCI_GENERIC,
  1294. .of_match = pci_generic_ids,
  1295. };
  1296. void pci_init(void)
  1297. {
  1298. struct udevice *bus;
  1299. /*
  1300. * Enumerate all known controller devices. Enumeration has the side-
  1301. * effect of probing them, so PCIe devices will be enumerated too.
  1302. */
  1303. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1304. bus;
  1305. uclass_next_device_check(&bus)) {
  1306. ;
  1307. }
  1308. }