otc570.c 10.0 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  4. * esd electronic system design gmbh <www.esd.eu>
  5. *
  6. * (C) Copyright 2007-2008
  7. * Stelian Pop <stelian.pop@leadtechdesign.com>
  8. * Lead Tech Design <www.leadtechdesign.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <asm/arch/at91sam9263.h>
  30. #include <asm/arch/at91sam9_matrix.h>
  31. #include <asm/arch/at91sam9_smc.h>
  32. #include <asm/arch/at91_common.h>
  33. #include <asm/arch/at91_pmc.h>
  34. #include <asm/arch/at91_rstc.h>
  35. #include <asm/arch/clk.h>
  36. #include <asm/arch/gpio.h>
  37. #include <asm/arch/hardware.h>
  38. #include <asm/arch/io.h>
  39. #include <atmel_lcdc.h>
  40. #include <lcd.h>
  41. #include <netdev.h>
  42. #ifdef CONFIG_LCD_INFO
  43. #include <nand.h>
  44. #include <version.h>
  45. #endif
  46. DECLARE_GLOBAL_DATA_PTR;
  47. /*
  48. * Miscelaneous platform dependent initialisations
  49. */
  50. static int hw_rev = -1; /* hardware revision */
  51. int get_hw_rev(void)
  52. {
  53. if (hw_rev >= 0)
  54. return hw_rev;
  55. hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
  56. hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
  57. hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
  58. hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
  59. if (hw_rev == 15)
  60. hw_rev = 0;
  61. return hw_rev;
  62. }
  63. #ifdef CONFIG_CMD_NAND
  64. static void otc570_nand_hw_init(void)
  65. {
  66. unsigned long csa;
  67. /* Enable CS3 */
  68. csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  69. at91_sys_write(AT91_MATRIX_EBI0CSA,
  70. csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  71. /* Configure SMC CS3 for NAND/SmartMedia */
  72. at91_sys_write(AT91_SMC_SETUP(3),
  73. AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  74. AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  75. at91_sys_write(AT91_SMC_PULSE(3),
  76. AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  77. AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  78. at91_sys_write(AT91_SMC_CYCLE(3),
  79. AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  80. at91_sys_write(AT91_SMC_MODE(3),
  81. AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  82. AT91_SMC_EXNWMODE_DISABLE |
  83. AT91_SMC_DBW_8 |
  84. AT91_SMC_TDF_(2));
  85. /* Configure RDY/BSY */
  86. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  87. /* Enable NandFlash */
  88. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  89. }
  90. #endif /* CONFIG_CMD_NAND */
  91. #ifdef CONFIG_MACB
  92. static void otc570_macb_hw_init(void)
  93. {
  94. /* Enable clock */
  95. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
  96. at91_macb_hw_init();
  97. }
  98. #endif
  99. /*
  100. * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  101. * controller debugging
  102. * The ET1100 is located at physical address 0x70000000
  103. * Its process memory is located at physical address 0x70001000
  104. */
  105. static void otc570_ethercat_hw_init(void)
  106. {
  107. /* Configure SMC EBI1_CS0 for EtherCAT */
  108. at91_sys_write(AT91_SMC1_SETUP(0),
  109. AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  110. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  111. at91_sys_write(AT91_SMC1_PULSE(0),
  112. AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
  113. AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
  114. at91_sys_write(AT91_SMC1_CYCLE(0),
  115. AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
  116. /*
  117. * Configure behavior at external wait signal, byte-select mode, 16 bit
  118. * data bus width, none data float wait states and TDF optimization
  119. */
  120. at91_sys_write(AT91_SMC1_MODE(0),
  121. AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
  122. AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
  123. AT91_SMC_TDFMODE);
  124. /* Configure RDY/BSY */
  125. at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
  126. }
  127. #ifdef CONFIG_LCD
  128. /* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
  129. vidinfo_t panel_info = {
  130. .vl_col = 640,
  131. .vl_row = 480,
  132. .vl_clk = 25175000,
  133. .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
  134. ATMEL_LCDC_INVFRAME_INVERTED,
  135. .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */
  136. .vl_tft = 1, /* 0 = passive, 1 = TFT */
  137. .vl_vsync_len = 1, /* Length of vertical sync in NOL */
  138. .vl_upper_margin = 35, /* Idle lines at the frame start */
  139. .vl_lower_margin = 5, /* Idle lines at the end of the frame */
  140. .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
  141. .vl_left_margin = 112, /* Idle cycles at the line beginning */
  142. .vl_right_margin = 1, /* Idle cycles at the end of the line */
  143. .mmio = AT91SAM9263_LCDC_BASE,
  144. };
  145. void lcd_enable(void)
  146. {
  147. at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
  148. }
  149. void lcd_disable(void)
  150. {
  151. at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
  152. }
  153. static void otc570_lcd_hw_init(void)
  154. {
  155. at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
  156. at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
  157. at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
  158. at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
  159. at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
  160. at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
  161. at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
  162. at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
  163. at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
  164. at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
  165. at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
  166. at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
  167. at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
  168. at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
  169. at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
  170. at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
  171. at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
  172. at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
  173. at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
  174. at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
  175. at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
  176. at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
  177. at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
  178. at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
  179. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
  180. gd->fb_base = CONFIG_OTC570_LCD_BASE;
  181. }
  182. #ifdef CONFIG_LCD_INFO
  183. void lcd_show_board_info(void)
  184. {
  185. ulong dram_size, nand_size;
  186. int i;
  187. char temp[32];
  188. dram_size = 0;
  189. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  190. dram_size += gd->bd->bi_dram[i].size;
  191. nand_size = 0;
  192. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  193. nand_size += nand_info[i].size;
  194. lcd_printf("\n%s\n", U_BOOT_VERSION);
  195. lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
  196. strmhz(temp, get_cpu_clk_rate()));
  197. lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
  198. dram_size >> 20,
  199. nand_size >> 20 );
  200. lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
  201. lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
  202. lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
  203. }
  204. #endif /* CONFIG_LCD_INFO */
  205. #endif /* CONFIG_LCD */
  206. int dram_init(void)
  207. {
  208. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  209. gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
  210. return 0;
  211. }
  212. int board_eth_init(bd_t *bis)
  213. {
  214. int rc = 0;
  215. #ifdef CONFIG_MACB
  216. rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
  217. #endif
  218. return rc;
  219. }
  220. int checkboard(void)
  221. {
  222. char str[32];
  223. puts("Board: esd ARM9 HMI Panel - OTC570");
  224. if (getenv_r("serial#", str, sizeof(str)) > 0) {
  225. puts(", serial# ");
  226. puts(str);
  227. }
  228. printf("\nHardware-revision: 1.%d\n", get_hw_rev());
  229. printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
  230. return 0;
  231. }
  232. #ifdef CONFIG_SERIAL_TAG
  233. void get_board_serial(struct tag_serialnr *serialnr)
  234. {
  235. char *str;
  236. char *serial = getenv("serial#");
  237. if (serial) {
  238. str = strchr(serial, '_');
  239. if (str && (strlen(str) >= 4)) {
  240. serialnr->high = (*(str + 1) << 8) | *(str + 2);
  241. serialnr->low = simple_strtoul(str + 3, NULL, 16);
  242. }
  243. } else {
  244. serialnr->high = 0;
  245. serialnr->low = 0;
  246. }
  247. }
  248. #endif
  249. #ifdef CONFIG_REVISION_TAG
  250. u32 get_board_rev(void)
  251. {
  252. return hw_rev | 0x100;
  253. }
  254. #endif
  255. #ifdef CONFIG_MISC_INIT_R
  256. int misc_init_r(void)
  257. {
  258. char str[64];
  259. at91_set_gpio_output(AT91_PIN_PA29, 1);
  260. at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
  261. at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
  262. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
  263. /* Set USART_MODE = 1 (RS485) */
  264. at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
  265. printf("USART0: ");
  266. if (getenv_r("usart0", str, sizeof(str)) == -1) {
  267. printf("No entry - assuming 1-wire\n");
  268. /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
  269. at91_set_gpio_output(AT91_PIN_PA29, 0);
  270. } else {
  271. if (strcmp(str, "1-wire") == 0) {
  272. printf("%s\n", str);
  273. at91_set_gpio_output(AT91_PIN_PA29, 0);
  274. } else if (strcmp(str, "rs485") == 0) {
  275. printf("%s\n", str);
  276. at91_set_gpio_output(AT91_PIN_PA29, 1);
  277. } else {
  278. printf("Wrong entry - assuming 1-wire ");
  279. printf("(valid values are '1-wire' or 'rs485')\n");
  280. at91_set_gpio_output(AT91_PIN_PA29, 0);
  281. }
  282. }
  283. printf("Display memory address: 0x%08lX\n", gd->fb_base);
  284. return 0;
  285. }
  286. #endif /* CONFIG_MISC_INIT_R */
  287. int board_init(void)
  288. {
  289. /* Peripheral Clock Enable Register */
  290. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
  291. 1 << AT91SAM9263_ID_PIOB |
  292. 1 << AT91SAM9263_ID_PIOCDE |
  293. 1 << AT91SAM9263_ID_TWI |
  294. 1 << AT91SAM9263_ID_SPI0 |
  295. 1 << AT91SAM9263_ID_LCDC |
  296. 1 << AT91SAM9263_ID_UHP);
  297. /* arch number of OTC570-Board */
  298. gd->bd->bi_arch_number = MACH_TYPE_OTC570;
  299. /* adress of boot parameters */
  300. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  301. at91_serial_hw_init();
  302. #ifdef CONFIG_CMD_NAND
  303. otc570_nand_hw_init();
  304. #endif
  305. otc570_ethercat_hw_init();
  306. #ifdef CONFIG_HAS_DATAFLASH
  307. at91_spi0_hw_init(1 << 0);
  308. #endif
  309. #ifdef CONFIG_MACB
  310. otc570_macb_hw_init();
  311. #endif
  312. #ifdef CONFIG_AT91_CAN
  313. at91_can_hw_init();
  314. #endif
  315. #ifdef CONFIG_USB_OHCI_NEW
  316. at91_uhp_hw_init();
  317. #endif
  318. #ifdef CONFIG_LCD
  319. otc570_lcd_hw_init();
  320. #endif
  321. return 0;
  322. }