ls2080a_common.h 9.8 KB

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  1. /*
  2. * Copyright (C) 2014 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __LS2_COMMON_H
  7. #define __LS2_COMMON_H
  8. #define CONFIG_REMAKE_ELF
  9. #define CONFIG_FSL_LAYERSCAPE
  10. #define CONFIG_FSL_LSCH3
  11. #define CONFIG_LS2080A
  12. #define CONFIG_MP
  13. #define CONFIG_GICV3
  14. #define CONFIG_FSL_TZPC_BP147
  15. /* Errata fixes */
  16. #define CONFIG_ARM_ERRATA_828024
  17. #define CONFIG_ARM_ERRATA_826974
  18. #include <asm/arch/ls2080a_stream_id.h>
  19. #include <asm/arch/config.h>
  20. #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
  21. #define CONFIG_SYS_HAS_SERDES
  22. #endif
  23. /* Link Definitions */
  24. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  25. /* We need architecture specific misc initializations */
  26. #define CONFIG_ARCH_MISC_INIT
  27. /* Link Definitions */
  28. #ifdef CONFIG_SPL
  29. #define CONFIG_SYS_TEXT_BASE 0x80400000
  30. #else
  31. #define CONFIG_SYS_TEXT_BASE 0x30100000
  32. #endif
  33. #ifdef CONFIG_EMU
  34. #define CONFIG_SYS_NO_FLASH
  35. #endif
  36. #define CONFIG_SUPPORT_RAW_INITRD
  37. #define CONFIG_SKIP_LOWLEVEL_INIT
  38. #define CONFIG_BOARD_EARLY_INIT_F 1
  39. /* Flat Device Tree Definitions */
  40. #define CONFIG_OF_LIBFDT
  41. #define CONFIG_OF_BOARD_SETUP
  42. #define CONFIG_OF_STDOUT_VIA_ALIAS
  43. /* new uImage format support */
  44. #define CONFIG_FIT
  45. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  46. #ifndef CONFIG_SPL
  47. #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
  48. #endif
  49. #ifndef CONFIG_SYS_FSL_DDR4
  50. #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
  51. #define CONFIG_SYS_DDR_RAW_TIMING
  52. #endif
  53. #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
  54. #define CONFIG_VERY_BIG_RAM
  55. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  56. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  57. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  58. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  59. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
  60. /*
  61. * SMP Definitinos
  62. */
  63. #define CPU_RELEASE_ADDR secondary_boot_func
  64. #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  65. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  66. #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
  67. /*
  68. * DDR controller use 0 as the base address for binding.
  69. * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  70. */
  71. #define CONFIG_SYS_DP_DDR_BASE_PHY 0
  72. #define CONFIG_DP_DDR_CTRL 2
  73. #define CONFIG_DP_DDR_NUM_CTRLS 1
  74. #endif
  75. /* Generic Timer Definitions */
  76. /*
  77. * This is not an accurate number. It is used in start.S. The frequency
  78. * will be udpated later when get_bus_freq(0) is available.
  79. */
  80. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  81. /* Size of malloc() pool */
  82. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  83. /* I2C */
  84. #define CONFIG_CMD_I2C
  85. #define CONFIG_SYS_I2C
  86. #define CONFIG_SYS_I2C_MXC
  87. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  88. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  89. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  90. #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
  91. /* Serial Port */
  92. #define CONFIG_CONS_INDEX 1
  93. #define CONFIG_SYS_NS16550_SERIAL
  94. #define CONFIG_SYS_NS16550_REG_SIZE 1
  95. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  96. #define CONFIG_BAUDRATE 115200
  97. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  98. /* IFC */
  99. #define CONFIG_FSL_IFC
  100. /*
  101. * During booting, IFC is mapped at the region of 0x30000000.
  102. * But this region is limited to 256MB. To accommodate NOR, promjet
  103. * and FPGA. This region is divided as below:
  104. * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  105. * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  106. * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  107. *
  108. * To accommodate bigger NOR flash and other devices, we will map IFC
  109. * chip selects to as below:
  110. * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  111. * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  112. * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  113. * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  114. * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  115. *
  116. * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  117. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  118. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  119. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  120. * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  121. */
  122. #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  123. #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  124. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  125. #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  126. #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  127. #ifndef CONFIG_SYS_NO_FLASH
  128. #define CONFIG_FLASH_CFI_DRIVER
  129. #define CONFIG_SYS_FLASH_CFI
  130. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  131. #define CONFIG_SYS_FLASH_QUIET_TEST
  132. #endif
  133. #ifndef __ASSEMBLY__
  134. unsigned long long get_qixis_addr(void);
  135. #endif
  136. #define QIXIS_BASE get_qixis_addr()
  137. #define QIXIS_BASE_PHYS 0x20000000
  138. #define QIXIS_BASE_PHYS_EARLY 0xC000000
  139. #define QIXIS_STAT_PRES1 0xb
  140. #define QIXIS_SDID_MASK 0x07
  141. #define QIXIS_ESDHC_NO_ADAPTER 0x7
  142. #define CONFIG_SYS_NAND_BASE 0x530000000ULL
  143. #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  144. /* Debug Server firmware */
  145. #define CONFIG_FSL_DEBUG_SERVER
  146. /* 2 sec timeout */
  147. #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
  148. /* MC firmware */
  149. #define CONFIG_FSL_MC_ENET
  150. /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  151. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  152. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  153. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  154. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  155. #ifndef CONFIG_LS2080A
  156. #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  157. #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  158. #endif
  159. /*
  160. * Carve out a DDR region which will not be used by u-boot/Linux
  161. *
  162. * It will be used by MC and Debug Server. The MC region must be
  163. * 512MB aligned, so the min size to hide is 512MB.
  164. */
  165. #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
  166. #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
  167. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
  168. #define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
  169. #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
  170. #endif
  171. /* PCIe */
  172. #define CONFIG_PCIE1 /* PCIE controler 1 */
  173. #define CONFIG_PCIE2 /* PCIE controler 2 */
  174. #define CONFIG_PCIE3 /* PCIE controler 3 */
  175. #define CONFIG_PCIE4 /* PCIE controler 4 */
  176. #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
  177. #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
  178. #define CONFIG_SYS_PCI_64BIT
  179. #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
  180. #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
  181. #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
  182. #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
  183. #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
  184. #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
  185. #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
  186. #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
  187. #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
  188. #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
  189. /* Command line configuration */
  190. #define CONFIG_CMD_CACHE
  191. #define CONFIG_CMD_DHCP
  192. #define CONFIG_CMD_ENV
  193. #define CONFIG_CMD_GREPENV
  194. #define CONFIG_CMD_MII
  195. #define CONFIG_CMD_PING
  196. /* Miscellaneous configurable options */
  197. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  198. #define CONFIG_ARCH_EARLY_INIT_R
  199. /* Physical Memory Map */
  200. /* fixme: these need to be checked against the board */
  201. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  202. #define CONFIG_NR_DRAM_BANKS 3
  203. #define CONFIG_HWCONFIG
  204. #define HWCONFIG_BUFFER_SIZE 128
  205. #define CONFIG_DISPLAY_CPUINFO
  206. /* Initial environment variables */
  207. #define CONFIG_EXTRA_ENV_SETTINGS \
  208. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  209. "loadaddr=0x80100000\0" \
  210. "kernel_addr=0x100000\0" \
  211. "ramdisk_addr=0x800000\0" \
  212. "ramdisk_size=0x2000000\0" \
  213. "fdt_high=0xa0000000\0" \
  214. "initrd_high=0xffffffffffffffff\0" \
  215. "kernel_start=0x581200000\0" \
  216. "kernel_load=0xa0000000\0" \
  217. "kernel_size=0x2800000\0" \
  218. "console=ttyAMA0,38400n8\0"
  219. #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
  220. "earlycon=uart8250,mmio,0x21c0500,115200 " \
  221. "ramdisk_size=0x2000000 default_hugepagesz=2m" \
  222. " hugepagesz=2m hugepages=16"
  223. #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
  224. "$kernel_size && bootm $kernel_load"
  225. #define CONFIG_BOOTDELAY 10
  226. /* Monitor Command Prompt */
  227. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  228. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  229. sizeof(CONFIG_SYS_PROMPT) + 16)
  230. #define CONFIG_SYS_HUSH_PARSER
  231. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  232. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  233. #define CONFIG_SYS_LONGHELP
  234. #define CONFIG_CMDLINE_EDITING 1
  235. #define CONFIG_AUTO_COMPLETE
  236. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  237. #ifndef __ASSEMBLY__
  238. unsigned long get_dram_size_to_hide(void);
  239. #endif
  240. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  241. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  242. #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
  243. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  244. #define CONFIG_SPL_ENV_SUPPORT
  245. #define CONFIG_SPL_FRAMEWORK
  246. #define CONFIG_SPL_I2C_SUPPORT
  247. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  248. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  249. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  250. #define CONFIG_SPL_MAX_SIZE 0x16000
  251. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  252. #define CONFIG_SPL_NAND_SUPPORT
  253. #define CONFIG_SPL_SERIAL_SUPPORT
  254. #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
  255. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  256. #define CONFIG_SPL_TEXT_BASE 0x1800a000
  257. #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
  258. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  259. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
  260. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  261. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  262. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  263. #endif /* __LS2_COMMON_H */