fsl_ddr_gen4.c 15 KB

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  1. /*
  2. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <asm/processor.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ddr.h>
  12. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  13. static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  14. {
  15. int timeout = 1000;
  16. ddr_out32(ptr, value);
  17. while (ddr_in32(ptr) & bits) {
  18. udelay(100);
  19. timeout--;
  20. }
  21. if (timeout <= 0)
  22. puts("Error: A007865 wait for clear timeout.\n");
  23. }
  24. #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
  25. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  26. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  27. #endif
  28. /*
  29. * regs has the to-be-set values for DDR controller registers
  30. * ctrl_num is the DDR controller number
  31. * step: 0 goes through the initialization in one pass
  32. * 1 sets registers and returns before enabling controller
  33. * 2 resumes from step 1 and continues to initialize
  34. * Dividing the initialization to two steps to deassert DDR reset signal
  35. * to comply with JEDEC specs for RDIMMs.
  36. */
  37. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  38. unsigned int ctrl_num, int step)
  39. {
  40. unsigned int i, bus_width;
  41. struct ccsr_ddr __iomem *ddr;
  42. u32 temp_sdram_cfg;
  43. u32 total_gb_size_per_controller;
  44. int timeout;
  45. #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  46. defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  47. u32 *eddrtqcr1;
  48. #endif
  49. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  50. u32 temp32, mr6;
  51. #endif
  52. #ifdef CONFIG_FSL_DDR_BIST
  53. u32 mtcr, err_detect, err_sbe;
  54. u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  55. #endif
  56. #ifdef CONFIG_FSL_DDR_BIST
  57. char buffer[CONFIG_SYS_CBSIZE];
  58. #endif
  59. switch (ctrl_num) {
  60. case 0:
  61. ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  62. #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  63. defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  64. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  65. #endif
  66. break;
  67. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  68. case 1:
  69. ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  70. #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  71. defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  72. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  73. #endif
  74. break;
  75. #endif
  76. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  77. case 2:
  78. ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  79. #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  80. defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  81. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  82. #endif
  83. break;
  84. #endif
  85. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  86. case 3:
  87. ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  88. #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  89. defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  90. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
  91. #endif
  92. break;
  93. #endif
  94. default:
  95. printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  96. return;
  97. }
  98. if (step == 2)
  99. goto step2;
  100. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  101. #ifdef CONFIG_LS2080A
  102. /* A008336 only applies to general DDR controllers */
  103. if ((ctrl_num == 0) || (ctrl_num == 1))
  104. #endif
  105. ddr_out32(eddrtqcr1, 0x63b30002);
  106. #endif
  107. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  108. #ifdef CONFIG_LS2080A
  109. /* A008514 only applies to DP-DDR controler */
  110. if (ctrl_num == 2)
  111. #endif
  112. ddr_out32(eddrtqcr1, 0x63b20002);
  113. #endif
  114. if (regs->ddr_eor)
  115. ddr_out32(&ddr->eor, regs->ddr_eor);
  116. ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  117. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  118. if (i == 0) {
  119. ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
  120. ddr_out32(&ddr->cs0_config, regs->cs[i].config);
  121. ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
  122. } else if (i == 1) {
  123. ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
  124. ddr_out32(&ddr->cs1_config, regs->cs[i].config);
  125. ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
  126. } else if (i == 2) {
  127. ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
  128. ddr_out32(&ddr->cs2_config, regs->cs[i].config);
  129. ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
  130. } else if (i == 3) {
  131. ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
  132. ddr_out32(&ddr->cs3_config, regs->cs[i].config);
  133. ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
  134. }
  135. }
  136. ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  137. ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  138. ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  139. ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  140. ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  141. ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  142. ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
  143. ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
  144. ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
  145. ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
  146. ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  147. ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
  148. ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
  149. ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
  150. ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
  151. ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
  152. ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  153. ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  154. ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  155. ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  156. ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  157. ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  158. ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  159. ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  160. ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
  161. ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
  162. ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
  163. ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
  164. ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
  165. ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
  166. ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
  167. ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
  168. ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  169. ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  170. ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
  171. ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  172. #ifndef CONFIG_SYS_FSL_DDR_EMU
  173. /*
  174. * Skip these two registers if running on emulator
  175. * because emulator doesn't have skew between bytes.
  176. */
  177. if (regs->ddr_wrlvl_cntl_2)
  178. ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
  179. if (regs->ddr_wrlvl_cntl_3)
  180. ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
  181. #endif
  182. ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  183. ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  184. ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  185. ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
  186. ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
  187. ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
  188. ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
  189. ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  190. #ifdef CONFIG_DEEP_SLEEP
  191. if (is_warm_boot()) {
  192. ddr_out32(&ddr->sdram_cfg_2,
  193. regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
  194. ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  195. ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
  196. /* DRAM VRef will not be trained */
  197. ddr_out32(&ddr->ddr_cdr2,
  198. regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
  199. } else
  200. #endif
  201. {
  202. ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  203. ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
  204. ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  205. ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  206. }
  207. ddr_out32(&ddr->err_disable, regs->err_disable);
  208. ddr_out32(&ddr->err_int_en, regs->err_int_en);
  209. for (i = 0; i < 32; i++) {
  210. if (regs->debug[i]) {
  211. debug("Write to debug_%d as %08x\n",
  212. i+1, regs->debug[i]);
  213. ddr_out32(&ddr->debug[i], regs->debug[i]);
  214. }
  215. }
  216. #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
  217. /* Erratum applies when accumulated ECC is used, or DBI is enabled */
  218. #define IS_ACC_ECC_EN(v) ((v) & 0x4)
  219. #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
  220. if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
  221. IS_DBI(regs->ddr_sdram_cfg_3))
  222. ddr_setbits32(ddr->debug[28], 0x9 << 20);
  223. #endif
  224. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  225. /* Part 1 of 2 */
  226. /* This erraum only applies to verion 5.2.0 */
  227. if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
  228. /* Disable DRAM VRef training */
  229. ddr_out32(&ddr->ddr_cdr2,
  230. regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
  231. /* Disable deskew */
  232. ddr_out32(&ddr->debug[28], 0x400);
  233. /* Disable D_INIT */
  234. ddr_out32(&ddr->sdram_cfg_2,
  235. regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
  236. ddr_out32(&ddr->debug[25], 0x9000);
  237. }
  238. #endif
  239. /*
  240. * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
  241. * deasserted. Clocks start when any chip select is enabled and clock
  242. * control register is set. Because all DDR components are connected to
  243. * one reset signal, this needs to be done in two steps. Step 1 is to
  244. * get the clocks started. Step 2 resumes after reset signal is
  245. * deasserted.
  246. */
  247. if (step == 1) {
  248. udelay(200);
  249. return;
  250. }
  251. step2:
  252. /* Set, but do not enable the memory */
  253. temp_sdram_cfg = regs->ddr_sdram_cfg;
  254. temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
  255. ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
  256. /*
  257. * 500 painful micro-seconds must elapse between
  258. * the DDR clock setup and the DDR config enable.
  259. * DDR2 need 200 us, and DDR3 need 500 us from spec,
  260. * we choose the max, that is 500 us for all of case.
  261. */
  262. udelay(500);
  263. mb();
  264. isb();
  265. #ifdef CONFIG_DEEP_SLEEP
  266. if (is_warm_boot()) {
  267. /* enter self-refresh */
  268. temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
  269. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  270. ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  271. /* do board specific memory setup */
  272. board_mem_sleep_setup();
  273. temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
  274. } else
  275. #endif
  276. temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
  277. /* Let the controller go */
  278. ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
  279. mb();
  280. isb();
  281. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  282. /* Part 2 of 2 */
  283. /* This erraum only applies to verion 5.2.0 */
  284. if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
  285. /* Wait for idle */
  286. timeout = 200;
  287. while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
  288. (timeout > 0)) {
  289. udelay(100);
  290. timeout--;
  291. }
  292. if (timeout <= 0) {
  293. printf("Controler %d timeout, debug_2 = %x\n",
  294. ctrl_num, ddr_in32(&ddr->debug[1]));
  295. }
  296. /* Set VREF */
  297. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  298. if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
  299. continue;
  300. mr6 = (regs->ddr_sdram_mode_10 >> 16) |
  301. MD_CNTL_MD_EN |
  302. MD_CNTL_CS_SEL(i) |
  303. MD_CNTL_MD_SEL(6) |
  304. 0x00200000;
  305. temp32 = mr6 | 0xc0;
  306. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  307. temp32, MD_CNTL_MD_EN);
  308. udelay(1);
  309. debug("MR6 = 0x%08x\n", temp32);
  310. temp32 = mr6 | 0xf0;
  311. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  312. temp32, MD_CNTL_MD_EN);
  313. udelay(1);
  314. debug("MR6 = 0x%08x\n", temp32);
  315. temp32 = mr6 | 0x70;
  316. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  317. temp32, MD_CNTL_MD_EN);
  318. udelay(1);
  319. debug("MR6 = 0x%08x\n", temp32);
  320. }
  321. ddr_out32(&ddr->sdram_md_cntl, 0);
  322. ddr_out32(&ddr->debug[28], 0); /* Enable deskew */
  323. ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
  324. /* wait for idle */
  325. timeout = 200;
  326. while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
  327. (timeout > 0)) {
  328. udelay(100);
  329. timeout--;
  330. }
  331. if (timeout <= 0) {
  332. printf("Controler %d timeout, debug_2 = %x\n",
  333. ctrl_num, ddr_in32(&ddr->debug[1]));
  334. }
  335. /* Restore D_INIT */
  336. ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  337. }
  338. #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
  339. total_gb_size_per_controller = 0;
  340. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  341. if (!(regs->cs[i].config & 0x80000000))
  342. continue;
  343. total_gb_size_per_controller += 1 << (
  344. ((regs->cs[i].config >> 14) & 0x3) + 2 +
  345. ((regs->cs[i].config >> 8) & 0x7) + 12 +
  346. ((regs->cs[i].config >> 4) & 0x3) + 0 +
  347. ((regs->cs[i].config >> 0) & 0x7) + 8 +
  348. 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
  349. 26); /* minus 26 (count of 64M) */
  350. }
  351. if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
  352. total_gb_size_per_controller *= 3;
  353. else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
  354. total_gb_size_per_controller <<= 1;
  355. /*
  356. * total memory / bus width = transactions needed
  357. * transactions needed / data rate = seconds
  358. * to add plenty of buffer, double the time
  359. * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
  360. * Let's wait for 800ms
  361. */
  362. bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
  363. >> SDRAM_CFG_DBW_SHIFT);
  364. timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
  365. (get_ddr_freq(ctrl_num) >> 20)) << 2;
  366. total_gb_size_per_controller >>= 4; /* shift down to gb size */
  367. debug("total %d GB\n", total_gb_size_per_controller);
  368. debug("Need to wait up to %d * 10ms\n", timeout);
  369. /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
  370. while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
  371. (timeout >= 0)) {
  372. udelay(10000); /* throttle polling rate */
  373. timeout--;
  374. }
  375. if (timeout <= 0)
  376. printf("Waiting for D_INIT timeout. Memory may not work.\n");
  377. #ifdef CONFIG_DEEP_SLEEP
  378. if (is_warm_boot()) {
  379. /* exit self-refresh */
  380. temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
  381. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  382. ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  383. }
  384. #endif
  385. #ifdef CONFIG_FSL_DDR_BIST
  386. #define BIST_PATTERN1 0xFFFFFFFF
  387. #define BIST_PATTERN2 0x0
  388. #define BIST_CR 0x80010000
  389. #define BIST_CR_EN 0x80000000
  390. #define BIST_CR_STAT 0x00000001
  391. #define CTLR_INTLV_MASK 0x20000000
  392. /* Perform build-in test on memory. Three-way interleaving is not yet
  393. * supported by this code. */
  394. if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
  395. puts("Running BIST test. This will take a while...");
  396. cs0_config = ddr_in32(&ddr->cs0_config);
  397. if (cs0_config & CTLR_INTLV_MASK) {
  398. cs0_bnds = ddr_in32(&cs0_bnds);
  399. cs1_bnds = ddr_in32(&cs1_bnds);
  400. cs2_bnds = ddr_in32(&cs2_bnds);
  401. cs3_bnds = ddr_in32(&cs3_bnds);
  402. /* set bnds to non-interleaving */
  403. ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
  404. ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
  405. ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
  406. ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
  407. }
  408. ddr_out32(&ddr->mtp1, BIST_PATTERN1);
  409. ddr_out32(&ddr->mtp2, BIST_PATTERN1);
  410. ddr_out32(&ddr->mtp3, BIST_PATTERN2);
  411. ddr_out32(&ddr->mtp4, BIST_PATTERN2);
  412. ddr_out32(&ddr->mtp5, BIST_PATTERN1);
  413. ddr_out32(&ddr->mtp6, BIST_PATTERN1);
  414. ddr_out32(&ddr->mtp7, BIST_PATTERN2);
  415. ddr_out32(&ddr->mtp8, BIST_PATTERN2);
  416. ddr_out32(&ddr->mtp9, BIST_PATTERN1);
  417. ddr_out32(&ddr->mtp10, BIST_PATTERN2);
  418. mtcr = BIST_CR;
  419. ddr_out32(&ddr->mtcr, mtcr);
  420. timeout = 100;
  421. while (timeout > 0 && (mtcr & BIST_CR_EN)) {
  422. mdelay(1000);
  423. timeout--;
  424. mtcr = ddr_in32(&ddr->mtcr);
  425. }
  426. if (timeout <= 0)
  427. puts("Timeout\n");
  428. else
  429. puts("Done\n");
  430. err_detect = ddr_in32(&ddr->err_detect);
  431. err_sbe = ddr_in32(&ddr->err_sbe);
  432. if (mtcr & BIST_CR_STAT) {
  433. printf("BIST test failed on controller %d.\n",
  434. ctrl_num);
  435. }
  436. if (err_detect || (err_sbe & 0xffff)) {
  437. printf("ECC error detected on controller %d.\n",
  438. ctrl_num);
  439. }
  440. if (cs0_config & CTLR_INTLV_MASK) {
  441. /* restore bnds registers */
  442. ddr_out32(&cs0_bnds, cs0_bnds);
  443. ddr_out32(&cs1_bnds, cs1_bnds);
  444. ddr_out32(&cs2_bnds, cs2_bnds);
  445. ddr_out32(&cs3_bnds, cs3_bnds);
  446. }
  447. }
  448. #endif
  449. }