ls2080ardb.c 6.1 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <netdev.h>
  10. #include <fsl_ifc.h>
  11. #include <fsl_ddr.h>
  12. #include <asm/io.h>
  13. #include <hwconfig.h>
  14. #include <fdt_support.h>
  15. #include <libfdt.h>
  16. #include <fsl_debug_server.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <environment.h>
  19. #include <i2c.h>
  20. #include <asm/arch/soc.h>
  21. #include "../common/qixis.h"
  22. #include "ls2080ardb_qixis.h"
  23. #define PIN_MUX_SEL_SDHC 0x00
  24. #define PIN_MUX_SEL_DSPI 0x0a
  25. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  26. DECLARE_GLOBAL_DATA_PTR;
  27. enum {
  28. MUX_TYPE_SDHC,
  29. MUX_TYPE_DSPI,
  30. };
  31. unsigned long long get_qixis_addr(void)
  32. {
  33. unsigned long long addr;
  34. if (gd->flags & GD_FLG_RELOC)
  35. addr = QIXIS_BASE_PHYS;
  36. else
  37. addr = QIXIS_BASE_PHYS_EARLY;
  38. /*
  39. * IFC address under 256MB is mapped to 0x30000000, any address above
  40. * is mapped to 0x5_10000000 up to 4GB.
  41. */
  42. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  43. return addr;
  44. }
  45. int checkboard(void)
  46. {
  47. u8 sw;
  48. char buf[15];
  49. cpu_name(buf);
  50. printf("Board: %s-RDB, ", buf);
  51. sw = QIXIS_READ(arch);
  52. printf("Board Arch: V%d, ", sw >> 4);
  53. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  54. sw = QIXIS_READ(brdcfg[0]);
  55. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  56. if (sw < 0x8)
  57. printf("vBank: %d\n", sw);
  58. else if (sw == 0x9)
  59. puts("NAND\n");
  60. else
  61. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  62. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  63. puts("SERDES1 Reference : ");
  64. printf("Clock1 = 156.25MHz ");
  65. printf("Clock2 = 156.25MHz");
  66. puts("\nSERDES2 Reference : ");
  67. printf("Clock1 = 100MHz ");
  68. printf("Clock2 = 100MHz\n");
  69. return 0;
  70. }
  71. unsigned long get_board_sys_clk(void)
  72. {
  73. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  74. switch (sysclk_conf & 0x0F) {
  75. case QIXIS_SYSCLK_83:
  76. return 83333333;
  77. case QIXIS_SYSCLK_100:
  78. return 100000000;
  79. case QIXIS_SYSCLK_125:
  80. return 125000000;
  81. case QIXIS_SYSCLK_133:
  82. return 133333333;
  83. case QIXIS_SYSCLK_150:
  84. return 150000000;
  85. case QIXIS_SYSCLK_160:
  86. return 160000000;
  87. case QIXIS_SYSCLK_166:
  88. return 166666666;
  89. }
  90. return 66666666;
  91. }
  92. int select_i2c_ch_pca9547(u8 ch)
  93. {
  94. int ret;
  95. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  96. if (ret) {
  97. puts("PCA: failed to select proper channel\n");
  98. return ret;
  99. }
  100. return 0;
  101. }
  102. int config_board_mux(int ctrl_type)
  103. {
  104. u8 reg5;
  105. reg5 = QIXIS_READ(brdcfg[5]);
  106. switch (ctrl_type) {
  107. case MUX_TYPE_SDHC:
  108. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  109. break;
  110. case MUX_TYPE_DSPI:
  111. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  112. break;
  113. default:
  114. printf("Wrong mux interface type\n");
  115. return -1;
  116. }
  117. QIXIS_WRITE(brdcfg[5], reg5);
  118. return 0;
  119. }
  120. int board_init(void)
  121. {
  122. char *env_hwconfig;
  123. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  124. u32 val;
  125. init_final_memctl_regs();
  126. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  127. env_hwconfig = getenv("hwconfig");
  128. if (hwconfig_f("dspi", env_hwconfig) &&
  129. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  130. config_board_mux(MUX_TYPE_DSPI);
  131. else
  132. config_board_mux(MUX_TYPE_SDHC);
  133. #ifdef CONFIG_ENV_IS_NOWHERE
  134. gd->env_addr = (ulong)&default_environment[0];
  135. #endif
  136. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  137. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
  138. return 0;
  139. }
  140. int board_early_init_f(void)
  141. {
  142. fsl_lsch3_early_init_f();
  143. return 0;
  144. }
  145. int misc_init_r(void)
  146. {
  147. if (hwconfig("sdhc"))
  148. config_board_mux(MUX_TYPE_SDHC);
  149. return 0;
  150. }
  151. void detail_board_ddr_info(void)
  152. {
  153. puts("\nDDR ");
  154. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  155. print_ddr_info(0);
  156. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  157. if (gd->bd->bi_dram[2].size) {
  158. puts("\nDP-DDR ");
  159. print_size(gd->bd->bi_dram[2].size, "");
  160. print_ddr_info(CONFIG_DP_DDR_CTRL);
  161. }
  162. #endif
  163. }
  164. int dram_init(void)
  165. {
  166. gd->ram_size = initdram(0);
  167. return 0;
  168. }
  169. #if defined(CONFIG_ARCH_MISC_INIT)
  170. int arch_misc_init(void)
  171. {
  172. #ifdef CONFIG_FSL_DEBUG_SERVER
  173. debug_server_init();
  174. #endif
  175. return 0;
  176. }
  177. #endif
  178. unsigned long get_dram_size_to_hide(void)
  179. {
  180. unsigned long dram_to_hide = 0;
  181. /* Carve the Debug Server private DRAM block from the end of DRAM */
  182. #ifdef CONFIG_FSL_DEBUG_SERVER
  183. dram_to_hide += debug_server_get_dram_block_size();
  184. #endif
  185. /* Carve the MC private DRAM block from the end of DRAM */
  186. #ifdef CONFIG_FSL_MC_ENET
  187. dram_to_hide += mc_get_dram_block_size();
  188. #endif
  189. return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
  190. }
  191. #ifdef CONFIG_FSL_MC_ENET
  192. void fdt_fixup_board_enet(void *fdt)
  193. {
  194. int offset;
  195. offset = fdt_path_offset(fdt, "/fsl-mc");
  196. if (offset < 0)
  197. offset = fdt_path_offset(fdt, "/fsl,dprc@0");
  198. if (offset < 0) {
  199. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  200. __func__, offset);
  201. return;
  202. }
  203. if (get_mc_boot_status() == 0)
  204. fdt_status_okay(fdt, offset);
  205. else
  206. fdt_status_fail(fdt, offset);
  207. }
  208. #endif
  209. #ifdef CONFIG_OF_BOARD_SETUP
  210. int ft_board_setup(void *blob, bd_t *bd)
  211. {
  212. int err;
  213. u64 base[CONFIG_NR_DRAM_BANKS];
  214. u64 size[CONFIG_NR_DRAM_BANKS];
  215. ft_cpu_setup(blob, bd);
  216. /* fixup DT for the two GPP DDR banks */
  217. base[0] = gd->bd->bi_dram[0].start;
  218. size[0] = gd->bd->bi_dram[0].size;
  219. base[1] = gd->bd->bi_dram[1].start;
  220. size[1] = gd->bd->bi_dram[1].size;
  221. fdt_fixup_memory_banks(blob, base, size, 2);
  222. #ifdef CONFIG_FSL_MC_ENET
  223. fdt_fixup_board_enet(blob);
  224. err = fsl_mc_ldpaa_exit(bd);
  225. if (err)
  226. return err;
  227. #endif
  228. return 0;
  229. }
  230. #endif
  231. void qixis_dump_switch(void)
  232. {
  233. int i, nr_of_cfgsw;
  234. QIXIS_WRITE(cms[0], 0x00);
  235. nr_of_cfgsw = QIXIS_READ(cms[1]);
  236. puts("DIP switch settings dump:\n");
  237. for (i = 1; i <= nr_of_cfgsw; i++) {
  238. QIXIS_WRITE(cms[0], i);
  239. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  240. }
  241. }
  242. /*
  243. * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
  244. * Both slots has 0x54, resulting 2nd slot unusable.
  245. */
  246. void update_spd_address(unsigned int ctrl_num,
  247. unsigned int slot,
  248. unsigned int *addr)
  249. {
  250. u8 sw;
  251. sw = QIXIS_READ(arch);
  252. if ((sw & 0xf) < 0x3) {
  253. if (ctrl_num == 1 && slot == 0)
  254. *addr = SPD_EEPROM_ADDRESS4;
  255. else if (ctrl_num == 1 && slot == 1)
  256. *addr = SPD_EEPROM_ADDRESS3;
  257. }
  258. }