eth_ls2080rdb.c 3.6 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <netdev.h>
  10. #include <malloc.h>
  11. #include <fsl_mdio.h>
  12. #include <miiphy.h>
  13. #include <phy.h>
  14. #include <fm_eth.h>
  15. #include <asm/io.h>
  16. #include <exports.h>
  17. #include <asm/arch/fsl_serdes.h>
  18. #include <fsl-mc/ldpaa_wriop.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int load_firmware_cortina(struct phy_device *phy_dev)
  21. {
  22. if (phy_dev->drv->config)
  23. return phy_dev->drv->config(phy_dev);
  24. return 0;
  25. }
  26. void load_phy_firmware(void)
  27. {
  28. int i;
  29. u8 phy_addr;
  30. struct phy_device *phy_dev;
  31. struct mii_dev *dev;
  32. phy_interface_t interface;
  33. /*Initialize and upload firmware for all the PHYs*/
  34. for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
  35. interface = wriop_get_enet_if(i);
  36. if (interface == PHY_INTERFACE_MODE_XGMII) {
  37. dev = wriop_get_mdio(i);
  38. phy_addr = wriop_get_phy_address(i);
  39. phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
  40. interface);
  41. if (!phy_dev) {
  42. printf("No phydev for phyaddr %d\n", phy_addr);
  43. continue;
  44. }
  45. /*Flash firmware for All CS4340 PHYS */
  46. if (phy_dev->phy_id == PHY_UID_CS4340)
  47. load_firmware_cortina(phy_dev);
  48. }
  49. }
  50. }
  51. int board_eth_init(bd_t *bis)
  52. {
  53. #if defined(CONFIG_FSL_MC_ENET)
  54. int i, interface;
  55. struct memac_mdio_info mdio_info;
  56. struct mii_dev *dev;
  57. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  58. u32 srds_s1;
  59. struct memac_mdio_controller *reg;
  60. srds_s1 = in_le32(&gur->rcwsr[28]) &
  61. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  62. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  63. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  64. mdio_info.regs = reg;
  65. mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  66. /* Register the EMI 1 */
  67. fm_memac_mdio_init(bis, &mdio_info);
  68. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  69. mdio_info.regs = reg;
  70. mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  71. /* Register the EMI 2 */
  72. fm_memac_mdio_init(bis, &mdio_info);
  73. switch (srds_s1) {
  74. case 0x2A:
  75. wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  76. wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  77. wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  78. wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  79. wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  80. wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  81. wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  82. wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  83. break;
  84. default:
  85. printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
  86. srds_s1);
  87. break;
  88. }
  89. for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
  90. interface = wriop_get_enet_if(i);
  91. switch (interface) {
  92. case PHY_INTERFACE_MODE_XGMII:
  93. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  94. wriop_set_mdio(i, dev);
  95. break;
  96. default:
  97. break;
  98. }
  99. }
  100. for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
  101. switch (wriop_get_enet_if(i)) {
  102. case PHY_INTERFACE_MODE_XGMII:
  103. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  104. wriop_set_mdio(i, dev);
  105. break;
  106. default:
  107. break;
  108. }
  109. }
  110. /* Load CORTINA CS4340 PHY firmware */
  111. load_phy_firmware();
  112. cpu_eth_init(bis);
  113. #endif /* CONFIG_FMAN_ENET */
  114. #ifdef CONFIG_PHY_AQUANTIA
  115. /*
  116. * Export functions to be used by AQ firmware
  117. * upload application
  118. */
  119. gd->jt->strcpy = strcpy;
  120. gd->jt->mdelay = mdelay;
  121. gd->jt->mdio_get_current_dev = mdio_get_current_dev;
  122. gd->jt->phy_find_by_mask = phy_find_by_mask;
  123. gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
  124. gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
  125. #endif
  126. return pci_eth_init(bis);
  127. }