ddr.h 2.3 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __DDR_H__
  7. #define __DDR_H__
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. };
  17. /*
  18. * These tables contain all valid speeds we want to override with board
  19. * specific parameters. datarate_mhz_high values need to be in ascending order
  20. * for each n_ranks group.
  21. */
  22. static const struct board_specific_parameters udimm0[] = {
  23. /*
  24. * memory controller 0
  25. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  26. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  27. */
  28. {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
  29. {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
  30. {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
  31. {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
  32. {}
  33. };
  34. /* DP-DDR DIMM */
  35. static const struct board_specific_parameters udimm2[] = {
  36. /*
  37. * memory controller 2
  38. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  39. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  40. */
  41. {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
  42. {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
  43. {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
  44. {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
  45. {}
  46. };
  47. static const struct board_specific_parameters rdimm0[] = {
  48. /*
  49. * memory controller 0
  50. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  51. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  52. */
  53. {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
  54. {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
  55. {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
  56. {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
  57. {}
  58. };
  59. /* DP-DDR DIMM */
  60. static const struct board_specific_parameters rdimm2[] = {
  61. /*
  62. * memory controller 2
  63. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  64. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  65. */
  66. {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
  67. {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
  68. {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
  69. {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
  70. {}
  71. };
  72. static const struct board_specific_parameters *udimms[] = {
  73. udimm0,
  74. udimm0,
  75. udimm2,
  76. };
  77. static const struct board_specific_parameters *rdimms[] = {
  78. rdimm0,
  79. rdimm0,
  80. rdimm2,
  81. };
  82. #endif