README 4.7 KB

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  1. Overview
  2. --------
  3. The LS2080A Reference Design (RDB) is a high-performance computing,
  4. evaluation, and development platform that supports the QorIQ LS2080A
  5. Layerscape Architecture processor.
  6. LS2080A SoC Overview
  7. ------------------
  8. The LS2080A integrated multicore processor combines eight ARM Cortex-A57
  9. processor cores with high-performance data path acceleration logic and network
  10. and peripheral bus interfaces required for networking, telecom/datacom,
  11. wireless infrastructure, and mil/aerospace applications.
  12. The LS2080A SoC includes the following function and features:
  13. - Eight 64-bit ARM Cortex-A57 CPUs
  14. - 1 MB platform cache with ECC
  15. - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
  16. - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
  17. the AIOP
  18. - Data path acceleration architecture (DPAA2) incorporating acceleration for
  19. the following functions:
  20. - Packet parsing, classification, and distribution (WRIOP)
  21. - Queue and Hardware buffer management for scheduling, packet sequencing, and
  22. congestion management, buffer allocation and de-allocation (QBMan)
  23. - Cryptography acceleration (SEC) at up to 10 Gbps
  24. - RegEx pattern matching acceleration (PME) at up to 10 Gbps
  25. - Decompression/compression acceleration (DCE) at up to 20 Gbps
  26. - Accelerated I/O processing (AIOP) at up to 20 Gbps
  27. - QDMA engine
  28. - 16 SerDes lanes at up to 10.3125 GHz
  29. - Ethernet interfaces
  30. - Up to eight 10 Gbps Ethernet MACs
  31. - Up to eight 1 / 2.5 Gbps Ethernet MACs
  32. - High-speed peripheral interfaces
  33. - Four PCIe 3.0 controllers, one supporting SR-IOV
  34. - Additional peripheral interfaces
  35. - Two serial ATA (SATA 3.0) controllers
  36. - Two high-speed USB 3.0 controllers with integrated PHY
  37. - Enhanced secure digital host controller (eSDXC/eMMC)
  38. - Serial peripheral interface (SPI) controller
  39. - Quad Serial Peripheral Interface (QSPI) Controller
  40. - Four I2C controllers
  41. - Two DUARTs
  42. - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
  43. - Support for hardware virtualization and partitioning enforcement
  44. - QorIQ platform's trust architecture 3.0
  45. - Service processor (SP) provides pre-boot initialization and secure-boot
  46. capabilities
  47. LS2080ARDB board Overview
  48. -----------------------
  49. - SERDES Connections, 16 lanes supporting:
  50. - PCI Express - 3.0
  51. - SATA 3.0
  52. - XFI
  53. - DDR Controller
  54. - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
  55. chip-selects and two DIMM connectors. Support is up to 2133MT/s.
  56. - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
  57. and two DIMM connectors. Support is up to 1600MT/s.
  58. -IFC/Local Bus
  59. - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
  60. - 128 MB NOR flash 16-bit data bus
  61. - One 2 GB NAND flash with ECC support
  62. - CPLD connection
  63. - USB 3.0
  64. - Two high speed USB 3.0 ports
  65. - First USB 3.0 port configured as Host with Type-A connector
  66. - Second USB 3.0 port configured as OTG with micro-AB connector
  67. - SDHC adapter
  68. - SD Card Rev 2.0 and Rev 3.0
  69. - DSPI
  70. - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
  71. - 4 I2C controllers
  72. - Two SATA onboard connectors
  73. - UART
  74. - ARM JTAG support
  75. Memory map from core's view
  76. ----------------------------
  77. 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
  78. 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
  79. 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
  80. 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
  81. 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
  82. 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
  83. 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
  84. Other addresses are either reserved, or not used directly by u-boot.
  85. This list should be updated when more addresses are used.
  86. IFC region map from core's view
  87. -------------------------------
  88. During boot i.e. IFC Region #1:-
  89. 0x30000000 - 0x37ffffff : 128MB : NOR flash
  90. 0x3C000000 - 0x40000000 : 64MB : CPLD
  91. After relocate to DDR i.e. IFC Region #2:-
  92. 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  93. 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
  94. 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  95. 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  96. 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  97. Booting Options
  98. ---------------
  99. a) NOR boot
  100. b) NAND boot
  101. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
  102. -------------------------------------------------------------------
  103. One needs to use appropriate bootargs to boot Linux flavors which do
  104. not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
  105. below:
  106. => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
  107. earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
  108. hugepages=16 mem=2048M'