ls2080aqds.c 6.7 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <netdev.h>
  10. #include <fsl_ifc.h>
  11. #include <fsl_ddr.h>
  12. #include <asm/io.h>
  13. #include <fdt_support.h>
  14. #include <libfdt.h>
  15. #include <fsl_debug_server.h>
  16. #include <fsl-mc/fsl_mc.h>
  17. #include <environment.h>
  18. #include <i2c.h>
  19. #include <rtc.h>
  20. #include <asm/arch/soc.h>
  21. #include <hwconfig.h>
  22. #include "../common/qixis.h"
  23. #include "ls2080aqds_qixis.h"
  24. #define PIN_MUX_SEL_SDHC 0x00
  25. #define PIN_MUX_SEL_DSPI 0x0a
  26. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  27. DECLARE_GLOBAL_DATA_PTR;
  28. enum {
  29. MUX_TYPE_SDHC,
  30. MUX_TYPE_DSPI,
  31. };
  32. unsigned long long get_qixis_addr(void)
  33. {
  34. unsigned long long addr;
  35. if (gd->flags & GD_FLG_RELOC)
  36. addr = QIXIS_BASE_PHYS;
  37. else
  38. addr = QIXIS_BASE_PHYS_EARLY;
  39. /*
  40. * IFC address under 256MB is mapped to 0x30000000, any address above
  41. * is mapped to 0x5_10000000 up to 4GB.
  42. */
  43. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  44. return addr;
  45. }
  46. int checkboard(void)
  47. {
  48. char buf[64];
  49. u8 sw;
  50. static const char *const freq[] = {"100", "125", "156.25",
  51. "100 separate SSCG"};
  52. int clock;
  53. cpu_name(buf);
  54. printf("Board: %s-QDS, ", buf);
  55. sw = QIXIS_READ(arch);
  56. printf("Board Arch: V%d, ", sw >> 4);
  57. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  58. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  59. sw = QIXIS_READ(brdcfg[0]);
  60. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  61. if (sw < 0x8)
  62. printf("vBank: %d\n", sw);
  63. else if (sw == 0x8)
  64. puts("PromJet\n");
  65. else if (sw == 0x9)
  66. puts("NAND\n");
  67. else if (sw == 0x15)
  68. printf("IFCCard\n");
  69. else
  70. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  71. printf("FPGA: v%d (%s), build %d",
  72. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  73. (int)qixis_read_minor());
  74. /* the timestamp string contains "\n" at the end */
  75. printf(" on %s", qixis_read_time(buf));
  76. /*
  77. * Display the actual SERDES reference clocks as configured by the
  78. * dip switches on the board. Note that the SWx registers could
  79. * technically be set to force the reference clocks to match the
  80. * values that the SERDES expects (or vice versa). For now, however,
  81. * we just display both values and hope the user notices when they
  82. * don't match.
  83. */
  84. puts("SERDES1 Reference : ");
  85. sw = QIXIS_READ(brdcfg[2]);
  86. clock = (sw >> 6) & 3;
  87. printf("Clock1 = %sMHz ", freq[clock]);
  88. clock = (sw >> 4) & 3;
  89. printf("Clock2 = %sMHz", freq[clock]);
  90. puts("\nSERDES2 Reference : ");
  91. clock = (sw >> 2) & 3;
  92. printf("Clock1 = %sMHz ", freq[clock]);
  93. clock = (sw >> 0) & 3;
  94. printf("Clock2 = %sMHz\n", freq[clock]);
  95. return 0;
  96. }
  97. unsigned long get_board_sys_clk(void)
  98. {
  99. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  100. switch (sysclk_conf & 0x0F) {
  101. case QIXIS_SYSCLK_83:
  102. return 83333333;
  103. case QIXIS_SYSCLK_100:
  104. return 100000000;
  105. case QIXIS_SYSCLK_125:
  106. return 125000000;
  107. case QIXIS_SYSCLK_133:
  108. return 133333333;
  109. case QIXIS_SYSCLK_150:
  110. return 150000000;
  111. case QIXIS_SYSCLK_160:
  112. return 160000000;
  113. case QIXIS_SYSCLK_166:
  114. return 166666666;
  115. }
  116. return 66666666;
  117. }
  118. unsigned long get_board_ddr_clk(void)
  119. {
  120. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  121. switch ((ddrclk_conf & 0x30) >> 4) {
  122. case QIXIS_DDRCLK_100:
  123. return 100000000;
  124. case QIXIS_DDRCLK_125:
  125. return 125000000;
  126. case QIXIS_DDRCLK_133:
  127. return 133333333;
  128. }
  129. return 66666666;
  130. }
  131. int select_i2c_ch_pca9547(u8 ch)
  132. {
  133. int ret;
  134. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  135. if (ret) {
  136. puts("PCA: failed to select proper channel\n");
  137. return ret;
  138. }
  139. return 0;
  140. }
  141. int config_board_mux(int ctrl_type)
  142. {
  143. u8 reg5;
  144. reg5 = QIXIS_READ(brdcfg[5]);
  145. switch (ctrl_type) {
  146. case MUX_TYPE_SDHC:
  147. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  148. break;
  149. case MUX_TYPE_DSPI:
  150. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  151. break;
  152. default:
  153. printf("Wrong mux interface type\n");
  154. return -1;
  155. }
  156. QIXIS_WRITE(brdcfg[5], reg5);
  157. return 0;
  158. }
  159. int board_init(void)
  160. {
  161. char *env_hwconfig;
  162. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  163. u32 val;
  164. init_final_memctl_regs();
  165. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  166. env_hwconfig = getenv("hwconfig");
  167. if (hwconfig_f("dspi", env_hwconfig) &&
  168. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  169. config_board_mux(MUX_TYPE_DSPI);
  170. else
  171. config_board_mux(MUX_TYPE_SDHC);
  172. #ifdef CONFIG_ENV_IS_NOWHERE
  173. gd->env_addr = (ulong)&default_environment[0];
  174. #endif
  175. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  176. rtc_enable_32khz_output();
  177. return 0;
  178. }
  179. int board_early_init_f(void)
  180. {
  181. fsl_lsch3_early_init_f();
  182. return 0;
  183. }
  184. void detail_board_ddr_info(void)
  185. {
  186. puts("\nDDR ");
  187. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  188. print_ddr_info(0);
  189. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  190. if (gd->bd->bi_dram[2].size) {
  191. puts("\nDP-DDR ");
  192. print_size(gd->bd->bi_dram[2].size, "");
  193. print_ddr_info(CONFIG_DP_DDR_CTRL);
  194. }
  195. #endif
  196. }
  197. int dram_init(void)
  198. {
  199. gd->ram_size = initdram(0);
  200. return 0;
  201. }
  202. #if defined(CONFIG_ARCH_MISC_INIT)
  203. int arch_misc_init(void)
  204. {
  205. #ifdef CONFIG_FSL_DEBUG_SERVER
  206. debug_server_init();
  207. #endif
  208. return 0;
  209. }
  210. #endif
  211. unsigned long get_dram_size_to_hide(void)
  212. {
  213. unsigned long dram_to_hide = 0;
  214. /* Carve the Debug Server private DRAM block from the end of DRAM */
  215. #ifdef CONFIG_FSL_DEBUG_SERVER
  216. dram_to_hide += debug_server_get_dram_block_size();
  217. #endif
  218. /* Carve the MC private DRAM block from the end of DRAM */
  219. #ifdef CONFIG_FSL_MC_ENET
  220. dram_to_hide += mc_get_dram_block_size();
  221. #endif
  222. return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
  223. }
  224. #ifdef CONFIG_FSL_MC_ENET
  225. void fdt_fixup_board_enet(void *fdt)
  226. {
  227. int offset;
  228. offset = fdt_path_offset(fdt, "/fsl-mc");
  229. if (offset < 0)
  230. offset = fdt_path_offset(fdt, "/fsl,dprc@0");
  231. if (offset < 0) {
  232. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  233. __func__, offset);
  234. return;
  235. }
  236. if (get_mc_boot_status() == 0)
  237. fdt_status_okay(fdt, offset);
  238. else
  239. fdt_status_fail(fdt, offset);
  240. }
  241. #endif
  242. #ifdef CONFIG_OF_BOARD_SETUP
  243. int ft_board_setup(void *blob, bd_t *bd)
  244. {
  245. int err;
  246. u64 base[CONFIG_NR_DRAM_BANKS];
  247. u64 size[CONFIG_NR_DRAM_BANKS];
  248. ft_cpu_setup(blob, bd);
  249. /* fixup DT for the two GPP DDR banks */
  250. base[0] = gd->bd->bi_dram[0].start;
  251. size[0] = gd->bd->bi_dram[0].size;
  252. base[1] = gd->bd->bi_dram[1].start;
  253. size[1] = gd->bd->bi_dram[1].size;
  254. fdt_fixup_memory_banks(blob, base, size, 2);
  255. #ifdef CONFIG_FSL_MC_ENET
  256. fdt_fixup_board_enet(blob);
  257. err = fsl_mc_ldpaa_exit(bd);
  258. if (err)
  259. return err;
  260. #endif
  261. return 0;
  262. }
  263. #endif
  264. void qixis_dump_switch(void)
  265. {
  266. int i, nr_of_cfgsw;
  267. QIXIS_WRITE(cms[0], 0x00);
  268. nr_of_cfgsw = QIXIS_READ(cms[1]);
  269. puts("DIP switch settings dump:\n");
  270. for (i = 1; i <= nr_of_cfgsw; i++) {
  271. QIXIS_WRITE(cms[0], i);
  272. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  273. }
  274. }