ddr.c 5.4 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. #include "ddr.h"
  10. DECLARE_GLOBAL_DATA_PTR;
  11. void fsl_ddr_board_options(memctl_options_t *popts,
  12. dimm_params_t *pdimm,
  13. unsigned int ctrl_num)
  14. {
  15. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  16. u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
  17. #endif
  18. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  19. ulong ddr_freq;
  20. int slot;
  21. if (ctrl_num > 2) {
  22. printf("Not supported controller number %d\n", ctrl_num);
  23. return;
  24. }
  25. for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
  26. if (pdimm[slot].n_ranks)
  27. break;
  28. }
  29. if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
  30. return;
  31. /*
  32. * we use identical timing for all slots. If needed, change the code
  33. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  34. */
  35. if (popts->registered_dimm_en)
  36. pbsp = rdimms[ctrl_num];
  37. else
  38. pbsp = udimms[ctrl_num];
  39. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  40. * freqency and n_banks specified in board_specific_parameters table.
  41. */
  42. ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  43. while (pbsp->datarate_mhz_high) {
  44. if (pbsp->n_ranks == pdimm[slot].n_ranks &&
  45. (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
  46. if (ddr_freq <= pbsp->datarate_mhz_high) {
  47. popts->clk_adjust = pbsp->clk_adjust;
  48. popts->wrlvl_start = pbsp->wrlvl_start;
  49. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  50. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  51. goto found;
  52. }
  53. pbsp_highest = pbsp;
  54. }
  55. pbsp++;
  56. }
  57. if (pbsp_highest) {
  58. printf("Error: board specific timing not found for data rate %lu MT/s\n"
  59. "Trying to use the highest speed (%u) parameters\n",
  60. ddr_freq, pbsp_highest->datarate_mhz_high);
  61. popts->clk_adjust = pbsp_highest->clk_adjust;
  62. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  63. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  64. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  65. } else {
  66. panic("DIMM is not supported by this board");
  67. }
  68. found:
  69. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  70. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  71. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  72. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  73. pbsp->wrlvl_ctl_3);
  74. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  75. if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  76. /* force DDR bus width to 32 bits */
  77. popts->data_bus_width = 1;
  78. popts->otf_burst_chop_en = 0;
  79. popts->burst_length = DDR_BL8;
  80. popts->bstopre = 0; /* enable auto precharge */
  81. /*
  82. * Layout optimization results byte mapping
  83. * Byte 0 -> Byte ECC
  84. * Byte 1 -> Byte 3
  85. * Byte 2 -> Byte 2
  86. * Byte 3 -> Byte 1
  87. * Byte ECC -> Byte 0
  88. */
  89. dq_mapping_0 = pdimm[slot].dq_mapping[0];
  90. dq_mapping_2 = pdimm[slot].dq_mapping[2];
  91. dq_mapping_3 = pdimm[slot].dq_mapping[3];
  92. pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
  93. pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
  94. pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
  95. pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
  96. pdimm[slot].dq_mapping[6] = dq_mapping_2;
  97. pdimm[slot].dq_mapping[7] = dq_mapping_3;
  98. pdimm[slot].dq_mapping[8] = dq_mapping_0;
  99. pdimm[slot].dq_mapping[9] = 0;
  100. pdimm[slot].dq_mapping[10] = 0;
  101. pdimm[slot].dq_mapping[11] = 0;
  102. pdimm[slot].dq_mapping[12] = 0;
  103. pdimm[slot].dq_mapping[13] = 0;
  104. pdimm[slot].dq_mapping[14] = 0;
  105. pdimm[slot].dq_mapping[15] = 0;
  106. pdimm[slot].dq_mapping[16] = 0;
  107. pdimm[slot].dq_mapping[17] = 0;
  108. }
  109. #endif
  110. /* To work at higher than 1333MT/s */
  111. popts->half_strength_driver_enable = 0;
  112. /*
  113. * Write leveling override
  114. */
  115. popts->wrlvl_override = 1;
  116. popts->wrlvl_sample = 0x0; /* 32 clocks */
  117. /*
  118. * Rtt and Rtt_WR override
  119. */
  120. popts->rtt_override = 0;
  121. /* Enable ZQ calibration */
  122. popts->zq_en = 1;
  123. if (ddr_freq < 2350) {
  124. popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  125. DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  126. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  127. DDR_CDR2_VREF_RANGE_2;
  128. } else {
  129. popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  130. DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
  131. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
  132. DDR_CDR2_VREF_RANGE_2;
  133. }
  134. }
  135. phys_size_t initdram(int board_type)
  136. {
  137. phys_size_t dram_size;
  138. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  139. return fsl_ddr_sdram_size();
  140. #else
  141. puts("Initializing DDR....using SPD\n");
  142. dram_size = fsl_ddr_sdram();
  143. #endif
  144. return dram_size;
  145. }
  146. void dram_init_banksize(void)
  147. {
  148. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  149. phys_size_t dp_ddr_size;
  150. #endif
  151. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  152. if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
  153. gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
  154. gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
  155. gd->bd->bi_dram[1].size = gd->ram_size -
  156. CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
  157. } else {
  158. gd->bd->bi_dram[0].size = gd->ram_size;
  159. }
  160. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  161. /* initialize DP-DDR here */
  162. puts("DP-DDR: ");
  163. /*
  164. * DDR controller use 0 as the base address for binding.
  165. * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  166. */
  167. dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
  168. CONFIG_DP_DDR_CTRL,
  169. CONFIG_DP_DDR_NUM_CTRLS,
  170. CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
  171. NULL, NULL, NULL);
  172. if (dp_ddr_size) {
  173. gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
  174. gd->bd->bi_dram[2].size = dp_ddr_size;
  175. } else {
  176. puts("Not detected");
  177. }
  178. #endif
  179. }