immap_lsch3.h 9.9 KB

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  1. /*
  2. * LayerScape Internal Memory Map
  3. *
  4. * Copyright 2014 Freescale Semiconductor, Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
  9. #define __ARCH_FSL_LSCH3_IMMAP_H_
  10. #define CONFIG_SYS_IMMR 0x01000000
  11. #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
  12. #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
  13. #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
  14. #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
  15. #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
  16. #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
  17. #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
  18. #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
  19. #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
  20. #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
  21. #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
  22. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
  23. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
  24. #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
  25. #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
  26. 0x18A0)
  27. #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
  28. #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
  29. #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
  30. #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
  31. /* SP (Cortex-A5) related */
  32. #define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
  33. #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
  34. #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
  35. #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
  36. (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
  37. #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
  38. (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
  39. #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
  40. #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
  41. #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
  42. #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
  43. #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
  44. #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
  45. #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
  46. #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
  47. #define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
  48. #define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
  49. /* TZ Address Space Controller Definitions */
  50. #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
  51. #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
  52. #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
  53. #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
  54. #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
  55. #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  56. #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  57. #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  58. #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  59. #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  60. #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  61. #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  62. #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  63. /* PCIe */
  64. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
  65. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
  66. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
  67. #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
  68. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
  69. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
  70. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
  71. #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
  72. /* Device Configuration */
  73. #define DCFG_BASE 0x01e00000
  74. #define DCFG_PORSR1 0x000
  75. #define DCFG_PORSR1_RCW_SRC 0xff800000
  76. #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
  77. #define DCFG_RCWSR13 0x130
  78. #define DCFG_RCWSR13_DSPI (0 << 8)
  79. #define DCFG_DCSR_BASE 0X700100000ULL
  80. #define DCFG_DCSR_PORCR1 0x000
  81. /* Supplemental Configuration */
  82. #define SCFG_BASE 0x01fc0000
  83. #define SCFG_USB3PRM1CR 0x000
  84. #define TP_ITYP_AV 0x00000001 /* Initiator available */
  85. #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
  86. #define TP_ITYP_TYPE_ARM 0x0
  87. #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
  88. #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
  89. #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
  90. #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
  91. #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
  92. #define TY_ITYP_VER_A7 0x1
  93. #define TY_ITYP_VER_A53 0x2
  94. #define TY_ITYP_VER_A57 0x3
  95. #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
  96. #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
  97. #define TP_INIT_PER_CLUSTER 4
  98. /* This is chassis generation 3 */
  99. struct sys_info {
  100. unsigned long freq_processor[CONFIG_MAX_CPUS];
  101. unsigned long freq_systembus;
  102. unsigned long freq_ddrbus;
  103. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  104. unsigned long freq_ddrbus2;
  105. #endif
  106. unsigned long freq_localbus;
  107. unsigned long freq_qe;
  108. #ifdef CONFIG_SYS_DPAA_FMAN
  109. unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  110. #endif
  111. #ifdef CONFIG_SYS_DPAA_QBMAN
  112. unsigned long freq_qman;
  113. #endif
  114. #ifdef CONFIG_SYS_DPAA_PME
  115. unsigned long freq_pme;
  116. #endif
  117. };
  118. /* Global Utilities Block */
  119. struct ccsr_gur {
  120. u32 porsr1; /* POR status 1 */
  121. u32 porsr2; /* POR status 2 */
  122. u8 res_008[0x20-0x8];
  123. u32 gpporcr1; /* General-purpose POR configuration */
  124. u32 gpporcr2; /* General-purpose POR configuration 2 */
  125. u32 dcfg_fusesr; /* Fuse status register */
  126. u32 gpporcr3;
  127. u32 gpporcr4;
  128. u8 res_034[0x70-0x34];
  129. u32 devdisr; /* Device disable control */
  130. u32 devdisr2; /* Device disable control 2 */
  131. u32 devdisr3; /* Device disable control 3 */
  132. u32 devdisr4; /* Device disable control 4 */
  133. u32 devdisr5; /* Device disable control 5 */
  134. u32 devdisr6; /* Device disable control 6 */
  135. u32 devdisr7; /* Device disable control 7 */
  136. #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
  137. #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
  138. #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
  139. #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
  140. #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
  141. #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
  142. #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
  143. #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
  144. #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
  145. #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
  146. #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
  147. #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
  148. #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
  149. #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
  150. #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
  151. #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
  152. #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
  153. #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
  154. #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
  155. #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
  156. #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
  157. #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
  158. #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
  159. #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
  160. u8 res_08c[0x90-0x8c];
  161. u32 coredisru; /* uppper portion for support of 64 cores */
  162. u32 coredisrl; /* lower portion for support of 64 cores */
  163. u8 res_098[0xa0-0x98];
  164. u32 pvr; /* Processor version */
  165. u32 svr; /* System version */
  166. u32 mvr; /* Manufacturing version */
  167. u8 res_0ac[0x100-0xac];
  168. u32 rcwsr[32]; /* Reset control word status */
  169. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
  170. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
  171. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
  172. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
  173. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
  174. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
  175. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
  176. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
  177. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
  178. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
  179. u8 res_180[0x200-0x180];
  180. u32 scratchrw[32]; /* Scratch Read/Write */
  181. u8 res_280[0x300-0x280];
  182. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  183. u8 res_310[0x400-0x310];
  184. u32 bootlocptrl; /* Boot location pointer low-order addr */
  185. u32 bootlocptrh; /* Boot location pointer high-order addr */
  186. u8 res_408[0x500-0x408];
  187. u8 res_500[0x740-0x500]; /* add more registers when needed */
  188. u32 tp_ityp[64]; /* Topology Initiator Type Register */
  189. struct {
  190. u32 upper;
  191. u32 lower;
  192. } tp_cluster[3]; /* Core Cluster n Topology Register */
  193. u8 res_858[0x1000-0x858];
  194. };
  195. struct ccsr_clk_cluster_group {
  196. struct {
  197. u8 res_00[0x10];
  198. u32 csr;
  199. u8 res_14[0x20-0x14];
  200. } hwncsr[3];
  201. u8 res_60[0x80-0x60];
  202. struct {
  203. u32 gsr;
  204. u8 res_84[0xa0-0x84];
  205. } pllngsr[3];
  206. u8 res_e0[0x100-0xe0];
  207. };
  208. struct ccsr_clk_ctrl {
  209. struct {
  210. u32 csr; /* core cluster n clock control status */
  211. u8 res_04[0x20-0x04];
  212. } clkcncsr[8];
  213. };
  214. struct ccsr_reset {
  215. u32 rstcr; /* 0x000 */
  216. u32 rstcrsp; /* 0x004 */
  217. u8 res_008[0x10-0x08]; /* 0x008 */
  218. u32 rstrqmr1; /* 0x010 */
  219. u32 rstrqmr2; /* 0x014 */
  220. u32 rstrqsr1; /* 0x018 */
  221. u32 rstrqsr2; /* 0x01c */
  222. u32 rstrqwdtmrl; /* 0x020 */
  223. u32 rstrqwdtmru; /* 0x024 */
  224. u8 res_028[0x30-0x28]; /* 0x028 */
  225. u32 rstrqwdtsrl; /* 0x030 */
  226. u32 rstrqwdtsru; /* 0x034 */
  227. u8 res_038[0x60-0x38]; /* 0x038 */
  228. u32 brrl; /* 0x060 */
  229. u32 brru; /* 0x064 */
  230. u8 res_068[0x80-0x68]; /* 0x068 */
  231. u32 pirset; /* 0x080 */
  232. u32 pirclr; /* 0x084 */
  233. u8 res_088[0x90-0x88]; /* 0x088 */
  234. u32 brcorenbr; /* 0x090 */
  235. u8 res_094[0x100-0x94]; /* 0x094 */
  236. u32 rcw_reqr; /* 0x100 */
  237. u32 rcw_completion; /* 0x104 */
  238. u8 res_108[0x110-0x108]; /* 0x108 */
  239. u32 pbi_reqr; /* 0x110 */
  240. u32 pbi_completion; /* 0x114 */
  241. u8 res_118[0xa00-0x118]; /* 0x118 */
  242. u32 qmbm_warmrst; /* 0xa00 */
  243. u32 soc_warmrst; /* 0xa04 */
  244. u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
  245. u32 ip_rev1; /* 0xbf8 */
  246. u32 ip_rev2; /* 0xbfc */
  247. };
  248. #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */