fsl_serdes.h 2.5 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __FSL_SERDES_H__
  7. #define __FSL_SERDES_H__
  8. #include <config.h>
  9. #if defined(CONFIG_LS2080A)
  10. enum srds_prtcl {
  11. NONE = 0,
  12. PCIE1,
  13. PCIE2,
  14. PCIE3,
  15. PCIE4,
  16. SATA1,
  17. SATA2,
  18. XAUI1,
  19. XAUI2,
  20. XFI1,
  21. XFI2,
  22. XFI3,
  23. XFI4,
  24. XFI5,
  25. XFI6,
  26. XFI7,
  27. XFI8,
  28. SGMII1,
  29. SGMII2,
  30. SGMII3,
  31. SGMII4,
  32. SGMII5,
  33. SGMII6,
  34. SGMII7,
  35. SGMII8,
  36. SGMII9,
  37. SGMII10,
  38. SGMII11,
  39. SGMII12,
  40. SGMII13,
  41. SGMII14,
  42. SGMII15,
  43. SGMII16,
  44. QSGMII_A, /* A indicates MACs 1-4 */
  45. QSGMII_B, /* B indicates MACs 5-8 */
  46. QSGMII_C, /* C indicates MACs 9-12 */
  47. QSGMII_D, /* D indicates MACs 12-16 */
  48. SERDES_PRCTL_COUNT
  49. };
  50. enum srds {
  51. FSL_SRDS_1 = 0,
  52. FSL_SRDS_2 = 1,
  53. };
  54. #elif defined(CONFIG_LS1043A)
  55. enum srds_prtcl {
  56. NONE = 0,
  57. PCIE1,
  58. PCIE2,
  59. PCIE3,
  60. PCIE4,
  61. SATA1,
  62. SATA2,
  63. SRIO1,
  64. SRIO2,
  65. SGMII_FM1_DTSEC1,
  66. SGMII_FM1_DTSEC2,
  67. SGMII_FM1_DTSEC3,
  68. SGMII_FM1_DTSEC4,
  69. SGMII_FM1_DTSEC5,
  70. SGMII_FM1_DTSEC6,
  71. SGMII_FM1_DTSEC9,
  72. SGMII_FM1_DTSEC10,
  73. SGMII_FM2_DTSEC1,
  74. SGMII_FM2_DTSEC2,
  75. SGMII_FM2_DTSEC3,
  76. SGMII_FM2_DTSEC4,
  77. SGMII_FM2_DTSEC5,
  78. SGMII_FM2_DTSEC6,
  79. SGMII_FM2_DTSEC9,
  80. SGMII_FM2_DTSEC10,
  81. SGMII_TSEC1,
  82. SGMII_TSEC2,
  83. SGMII_TSEC3,
  84. SGMII_TSEC4,
  85. XAUI_FM1,
  86. XAUI_FM2,
  87. AURORA,
  88. CPRI1,
  89. CPRI2,
  90. CPRI3,
  91. CPRI4,
  92. CPRI5,
  93. CPRI6,
  94. CPRI7,
  95. CPRI8,
  96. XAUI_FM1_MAC9,
  97. XAUI_FM1_MAC10,
  98. XAUI_FM2_MAC9,
  99. XAUI_FM2_MAC10,
  100. HIGIG_FM1_MAC9,
  101. HIGIG_FM1_MAC10,
  102. HIGIG_FM2_MAC9,
  103. HIGIG_FM2_MAC10,
  104. QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
  105. QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
  106. QSGMII_FM2_A,
  107. QSGMII_FM2_B,
  108. XFI_FM1_MAC1,
  109. XFI_FM1_MAC2,
  110. XFI_FM1_MAC9,
  111. XFI_FM1_MAC10,
  112. XFI_FM2_MAC9,
  113. XFI_FM2_MAC10,
  114. INTERLAKEN,
  115. QSGMII_SW1_A, /* Indicates ports on L2 Switch */
  116. QSGMII_SW1_B,
  117. SGMII_2500_FM1_DTSEC1,
  118. SGMII_2500_FM1_DTSEC2,
  119. SGMII_2500_FM1_DTSEC3,
  120. SGMII_2500_FM1_DTSEC4,
  121. SGMII_2500_FM1_DTSEC5,
  122. SGMII_2500_FM1_DTSEC6,
  123. SGMII_2500_FM1_DTSEC9,
  124. SGMII_2500_FM1_DTSEC10,
  125. SGMII_2500_FM2_DTSEC1,
  126. SGMII_2500_FM2_DTSEC2,
  127. SGMII_2500_FM2_DTSEC3,
  128. SGMII_2500_FM2_DTSEC4,
  129. SGMII_2500_FM2_DTSEC5,
  130. SGMII_2500_FM2_DTSEC6,
  131. SGMII_2500_FM2_DTSEC9,
  132. SGMII_2500_FM2_DTSEC10,
  133. SERDES_PRCTL_COUNT
  134. };
  135. enum srds {
  136. FSL_SRDS_1 = 0,
  137. };
  138. #endif
  139. int is_serdes_configured(enum srds_prtcl device);
  140. void fsl_serdes_init(void);
  141. int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
  142. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
  143. int is_serdes_prtcl_valid(int serdes, u32 prtcl);
  144. #ifdef CONFIG_LS1043A
  145. const char *serdes_clock_to_string(u32 clock);
  146. int get_serdes_protocol(void);
  147. #endif
  148. #endif /* __FSL_SERDES_H__ */