ls2080a_serdes.c 3.4 KB

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  1. /*
  2. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/arch/fsl_serdes.h>
  8. struct serdes_config {
  9. u8 protocol;
  10. u8 lanes[SRDS_MAX_LANES];
  11. };
  12. static struct serdes_config serdes1_cfg_tbl[] = {
  13. /* SerDes 1 */
  14. {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
  15. {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
  16. {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  17. SGMII1 } },
  18. {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  19. SGMII1 } },
  20. {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  21. SGMII1 } },
  22. {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  23. SGMII1 } },
  24. {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
  25. SGMII1 } },
  26. {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
  27. {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
  28. {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
  29. {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
  30. {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
  31. {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
  32. QSGMII_B} },
  33. {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
  34. {}
  35. };
  36. static struct serdes_config serdes2_cfg_tbl[] = {
  37. /* SerDes 2 */
  38. {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  39. SGMII16 } },
  40. {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  41. SGMII16 } },
  42. {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  43. SGMII16 } },
  44. {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  45. SGMII16 } },
  46. {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
  47. SGMII16 } },
  48. {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  49. {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
  50. {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  51. {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
  52. {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  53. {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
  54. {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
  55. {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
  56. {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
  57. SGMII16 } },
  58. {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
  59. PCIE4 } },
  60. {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
  61. SATA2 } },
  62. {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
  63. SATA2 } },
  64. {}
  65. };
  66. static struct serdes_config *serdes_cfg_tbl[] = {
  67. serdes1_cfg_tbl,
  68. serdes2_cfg_tbl,
  69. };
  70. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  71. {
  72. struct serdes_config *ptr;
  73. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  74. return 0;
  75. ptr = serdes_cfg_tbl[serdes];
  76. while (ptr->protocol) {
  77. if (ptr->protocol == cfg)
  78. return ptr->lanes[lane];
  79. ptr++;
  80. }
  81. return 0;
  82. }
  83. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  84. {
  85. int i;
  86. struct serdes_config *ptr;
  87. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  88. return 0;
  89. ptr = serdes_cfg_tbl[serdes];
  90. while (ptr->protocol) {
  91. if (ptr->protocol == prtcl)
  92. break;
  93. ptr++;
  94. }
  95. if (!ptr->protocol)
  96. return 0;
  97. for (i = 0; i < SRDS_MAX_LANES; i++) {
  98. if (ptr->lanes[i] != NONE)
  99. return 1;
  100. }
  101. return 0;
  102. }