README.lsch3 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305
  1. #
  2. # Copyright 2014-2015 Freescale Semiconductor
  3. #
  4. # SPDX-License-Identifier: GPL-2.0+
  5. #
  6. Freescale LayerScape with Chassis Generation 3
  7. This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
  8. for example LS2080A.
  9. DDR Layout
  10. ============
  11. Entire DDR region splits into two regions.
  12. - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
  13. - Region 2 is at 0x80_8000_0000 to the top of total memory,
  14. for example 16GB, 0x83_ffff_ffff.
  15. All DDR memory is marked as cache-enabled.
  16. When MC and Debug server is enabled, they carve 512MB away from the high
  17. end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
  18. with MC and Debug server enabled. Linux only sees 15.5GB.
  19. The reserved 512MB layout looks like
  20. +---------------+ <-- top/end of memory
  21. | 256MB | debug server
  22. +---------------+
  23. | 256MB | MC
  24. +---------------+
  25. | ... |
  26. MC requires the memory to be aligned with 512MB, so even debug server is
  27. not enabled, 512MB is reserved, not 256MB.
  28. Flash Layout
  29. ============
  30. (1) A typical layout of various images (including Linux and other firmware images)
  31. is shown below considering a 32MB NOR flash device present on most
  32. pre-silicon platforms (simulator and emulator):
  33. -------------------------
  34. | FIT Image |
  35. | (linux + DTB + RFS) |
  36. ------------------------- ----> 0x0120_0000
  37. | Debug Server FW |
  38. ------------------------- ----> 0x00C0_0000
  39. | AIOP FW |
  40. ------------------------- ----> 0x0070_0000
  41. | MC FW |
  42. ------------------------- ----> 0x006C_0000
  43. | MC DPL Blob |
  44. ------------------------- ----> 0x0020_0000
  45. | BootLoader + Env|
  46. ------------------------- ----> 0x0000_1000
  47. | PBI |
  48. ------------------------- ----> 0x0000_0080
  49. | RCW |
  50. ------------------------- ----> 0x0000_0000
  51. 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
  52. (2) A typical layout of various images (including Linux and other firmware images)
  53. is shown below considering a 128MB NOR flash device present on QDS and RDB
  54. boards:
  55. ----------------------------------------- ----> 0x5_8800_0000 ---
  56. | .. Unused .. (7M) | |
  57. ----------------------------------------- ----> 0x5_8790_0000 |
  58. | FIT Image (linux + DTB + RFS) (40M) | |
  59. ----------------------------------------- ----> 0x5_8510_0000 |
  60. | PHY firmware (2M) | |
  61. ----------------------------------------- ----> 0x5_84F0_0000 | 64K
  62. | Debug Server FW (2M) | | Alt
  63. ----------------------------------------- ----> 0x5_84D0_0000 | Bank
  64. | AIOP FW (4M) | |
  65. ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
  66. | MC DPC Blob (1M) | |
  67. ----------------------------------------- ----> 0x5_8480_0000 |
  68. | MC DPL Blob (1M) | |
  69. ----------------------------------------- ----> 0x5_8470_0000 |
  70. | MC FW (4M) | |
  71. ----------------------------------------- ----> 0x5_8430_0000 |
  72. | BootLoader Environment (1M) | |
  73. ----------------------------------------- ----> 0x5_8420_0000 |
  74. | BootLoader (1M) | |
  75. ----------------------------------------- ----> 0x5_8410_0000 |
  76. | RCW and PBI (1M) | |
  77. ----------------------------------------- ----> 0x5_8400_0000 ---
  78. | .. Unused .. (7M) | |
  79. ----------------------------------------- ----> 0x5_8390_0000 |
  80. | FIT Image (linux + DTB + RFS) (40M) | |
  81. ----------------------------------------- ----> 0x5_8110_0000 |
  82. | PHY firmware (2M) | |
  83. ----------------------------------------- ----> 0x5_80F0_0000 | 64K
  84. | Debug Server FW (2M) | | Bank
  85. ----------------------------------------- ----> 0x5_80D0_0000 |
  86. | AIOP FW (4M) | |
  87. ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
  88. | MC DPC Blob (1M) | |
  89. ----------------------------------------- ----> 0x5_8080_0000 |
  90. | MC DPL Blob (1M) | |
  91. ----------------------------------------- ----> 0x5_8070_0000 |
  92. | MC FW (4M) | |
  93. ----------------------------------------- ----> 0x5_8030_0000 |
  94. | BootLoader Environment (1M) | |
  95. ----------------------------------------- ----> 0x5_8020_0000 |
  96. | BootLoader (1M) | |
  97. ----------------------------------------- ----> 0x5_8010_0000 |
  98. | RCW and PBI (1M) | |
  99. ----------------------------------------- ----> 0x5_8000_0000 ---
  100. 128-MB NOR flash layout for QDS and RDB boards
  101. Environment Variables
  102. =====================
  103. mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
  104. the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
  105. mcmemsize: MC DRAM block size. If this variable is not defined, the value
  106. CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
  107. Booting from NAND
  108. -------------------
  109. Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
  110. The difference between NAND boot RCW image and NOR boot image is the PBI
  111. command sequence. Below is one example for PBI commands for QDS which uses
  112. NAND device with 2KB/page, block size 128KB.
  113. 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
  114. 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
  115. The above two commands set bootloc register to 0x00000000_1800a000 where
  116. the u-boot code will be running in OCRAM.
  117. 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
  118. BLOCK_SIZE=0x00014000
  119. This command copies u-boot image from NAND device into OCRAM. The values need
  120. to adjust accordingly.
  121. SRC should match the cfg_rcw_src, the reset config pins. It depends
  122. on the NAND device. See reference manual for cfg_rcw_src.
  123. SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
  124. the example above, 128KB. For easy maintenance, we put it at
  125. the beginning of next block from RCW.
  126. DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
  127. BLOCK_SIZE is the size to be copied by PBI.
  128. RCW image should be written to the beginning of NAND device. Example of using
  129. u-boot command
  130. nand write <rcw image in memory> 0 <size of rcw image>
  131. To form the NAND image, build u-boot with NAND config, for example,
  132. ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
  133. The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
  134. nand write <u-boot image in memory> 200000 <size of u-boot image>
  135. With these two images in NAND device, the board can boot from NAND.
  136. Another example for RDB boards,
  137. 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
  138. 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
  139. 3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
  140. BLOCK_SIZE=0x00014000
  141. nand write <rcw image in memory> 0 <size of rcw image>
  142. nand write <u-boot image in memory> 80000 <size of u-boot image>
  143. Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
  144. to match board NAND device with 4KB/page, block size 512KB.
  145. MMU Translation Tables
  146. ======================
  147. (1) Early MMU Tables:
  148. Level 0 Level 1 Level 2
  149. ------------------ ------------------ ------------------
  150. | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
  151. ------------------ ------------------ ------------------
  152. | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
  153. ------------------ | ------------------ ------------------
  154. | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
  155. ------------------ | ------------------ ------------------
  156. | | 0x00_c000_0000 | | 0x00_0060_0000 |
  157. | ------------------ ------------------
  158. | | 0x01_0000_0000 | | 0x00_0080_0000 |
  159. | ------------------ ------------------
  160. | ... ...
  161. | ------------------
  162. | | 0x05_8000_0000 | --|
  163. | ------------------ |
  164. | | 0x05_c000_0000 | |
  165. | ------------------ |
  166. | ... |
  167. | ------------------ | ------------------
  168. |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
  169. ------------------ ------------------
  170. | 0x80_4000_0000 | | 0x00_3020_0000 |
  171. ------------------ ------------------
  172. | 0x80_8000_0000 | | 0x00_3040_0000 |
  173. ------------------ ------------------
  174. | 0x80_c000_0000 | | 0x00_3060_0000 |
  175. ------------------ ------------------
  176. | 0x81_0000_0000 | | 0x00_3080_0000 |
  177. ------------------ ------------------
  178. ... ...
  179. (2) Final MMU Tables:
  180. Level 0 Level 1 Level 2
  181. ------------------ ------------------ ------------------
  182. | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
  183. ------------------ ------------------ ------------------
  184. | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
  185. ------------------ | ------------------ ------------------
  186. | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
  187. ------------------ | ------------------ ------------------
  188. | | 0x00_c000_0000 | | 0x00_0060_0000 |
  189. | ------------------ ------------------
  190. | | 0x01_0000_0000 | | 0x00_0080_0000 |
  191. | ------------------ ------------------
  192. | ... ...
  193. | ------------------
  194. | | 0x08_0000_0000 | --|
  195. | ------------------ |
  196. | | 0x08_4000_0000 | |
  197. | ------------------ |
  198. | ... |
  199. | ------------------ | ------------------
  200. |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
  201. ------------------ ------------------
  202. | 0x80_4000_0000 | | 0x08_0020_0000 |
  203. ------------------ ------------------
  204. | 0x80_8000_0000 | | 0x08_0040_0000 |
  205. ------------------ ------------------
  206. | 0x80_c000_0000 | | 0x08_0060_0000 |
  207. ------------------ ------------------
  208. | 0x81_0000_0000 | | 0x08_0080_0000 |
  209. ------------------ ------------------
  210. ... ...
  211. DPAA2 commands to manage Management Complex (MC)
  212. ------------------------------------------------
  213. DPAA2 commands has been introduced to manage Management Complex
  214. (MC). These commands are used to start mc, aiop and apply DPL
  215. from u-boot command prompt.
  216. Please note Management complex Firmware(MC), DPL and DPC are no
  217. more deployed during u-boot boot-sequence.
  218. Commands:
  219. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  220. b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  221. c) fsl_mc start aiop <FW_addr> - Start AIOP
  222. How to use commands :-
  223. 1. Command sequence for u-boot ethernet:
  224. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  225. b) DPMAC net-devices are now available for use
  226. Example-
  227. Assumption: MC firmware, DPL and DPC dtb is already programmed
  228. on NOR flash.
  229. => fsl_mc start mc 580300000 580800000
  230. => setenv ethact DPMAC1@xgmii
  231. => ping $serverip
  232. 2. Command sequence for Linux boot:
  233. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  234. b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  235. c) No DPMAC net-devices are available for use in u-boot
  236. d) boot Linux
  237. Example-
  238. Assumption: MC firmware, DPL and DPC dtb is already programmed
  239. on NOR flash.
  240. => fsl_mc start mc 580300000 580800000
  241. => setenv ethact DPMAC1@xgmii
  242. => tftp a0000000 kernel.itb
  243. => fsl_mc apply dpl 580700000
  244. => bootm a0000000
  245. 3. Command sequence for AIOP boot:
  246. a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
  247. b) fsl_mc start aiop <FW_addr> - Start AIOP
  248. c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
  249. d) No DPMAC net-devices are availabe for use in u-boot
  250. Please note actual AIOP start will happen during DPL parsing of
  251. Management complex
  252. Example-
  253. Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
  254. programmed on NOR flash.
  255. => fsl_mc start mc 580300000 580800000
  256. => fsl_mc start aiop 0x580900000
  257. => setenv ethact DPMAC1@xgmii
  258. => fsl_mc apply dpl 580700000