board-gx.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/gx.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/arch/meson-vpu.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/armv8/mmu.h>
  17. #include <linux/sizes.h>
  18. #include <usb.h>
  19. #include <linux/usb/otg.h>
  20. #include <asm/arch/usb-gx.h>
  21. #include <usb/dwc2_udc.h>
  22. #include <clk.h>
  23. #include <phy.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int meson_get_boot_device(void)
  26. {
  27. return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  28. }
  29. /* Configure the reserved memory zones exported by the secure registers
  30. * into EFI and DTB reserved memory entries.
  31. */
  32. void meson_init_reserved_memory(void *fdt)
  33. {
  34. u64 bl31_size, bl31_start;
  35. u64 bl32_size, bl32_start;
  36. u32 reg;
  37. /*
  38. * Get ARM Trusted Firmware reserved memory zones in :
  39. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  40. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  41. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  42. */
  43. reg = readl(GX_AO_SEC_GP_CFG3);
  44. bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  45. >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  46. bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  47. bl31_start = readl(GX_AO_SEC_GP_CFG5);
  48. bl32_start = readl(GX_AO_SEC_GP_CFG4);
  49. /*
  50. * Early Meson GX Firmware revisions did not provide the reserved
  51. * memory zones in the registers, keep fixed memory zone handling.
  52. */
  53. if (IS_ENABLED(CONFIG_MESON_GX) &&
  54. !reg && !bl31_start && !bl32_start) {
  55. bl31_start = 0x10000000;
  56. bl31_size = 0x200000;
  57. }
  58. /* Add first 16MiB reserved zone */
  59. meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  60. /* Add BL31 reserved zone */
  61. if (bl31_start && bl31_size)
  62. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  63. /* Add BL32 reserved zone */
  64. if (bl32_start && bl32_size)
  65. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  66. #if defined(CONFIG_VIDEO_MESON)
  67. meson_vpu_rsv_fb(fdt);
  68. #endif
  69. }
  70. phys_size_t get_effective_memsize(void)
  71. {
  72. /* Size is reported in MiB, convert it in bytes */
  73. return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  74. >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  75. }
  76. static struct mm_region gx_mem_map[] = {
  77. {
  78. .virt = 0x0UL,
  79. .phys = 0x0UL,
  80. .size = 0xc0000000UL,
  81. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  82. PTE_BLOCK_INNER_SHARE
  83. }, {
  84. .virt = 0xc0000000UL,
  85. .phys = 0xc0000000UL,
  86. .size = 0x30000000UL,
  87. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  88. PTE_BLOCK_NON_SHARE |
  89. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  90. }, {
  91. /* List terminator */
  92. 0,
  93. }
  94. };
  95. struct mm_region *mem_map = gx_mem_map;
  96. /* Configure the Ethernet MAC with the requested interface mode
  97. * with some optional flags.
  98. */
  99. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  100. {
  101. switch (mode) {
  102. case PHY_INTERFACE_MODE_RGMII:
  103. case PHY_INTERFACE_MODE_RGMII_ID:
  104. case PHY_INTERFACE_MODE_RGMII_RXID:
  105. case PHY_INTERFACE_MODE_RGMII_TXID:
  106. /* Set RGMII mode */
  107. setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
  108. GX_ETH_REG_0_TX_PHASE(1) |
  109. GX_ETH_REG_0_TX_RATIO(4) |
  110. GX_ETH_REG_0_PHY_CLK_EN |
  111. GX_ETH_REG_0_CLK_EN);
  112. /* Reset to external PHY */
  113. if(!IS_ENABLED(CONFIG_MESON_GXBB))
  114. writel(0x2009087f, GX_ETH_REG_3);
  115. break;
  116. case PHY_INTERFACE_MODE_RMII:
  117. /* Set RMII mode */
  118. out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
  119. GX_ETH_REG_0_CLK_EN);
  120. /* Use GXL RMII Internal PHY (also on GXM) */
  121. if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
  122. if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
  123. writel(0x10110181, GX_ETH_REG_2);
  124. writel(0xe40908ff, GX_ETH_REG_3);
  125. } else
  126. writel(0x2009087f, GX_ETH_REG_3);
  127. }
  128. break;
  129. default:
  130. printf("Invalid Ethernet interface mode\n");
  131. return;
  132. }
  133. /* Enable power gate */
  134. clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
  135. }
  136. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
  137. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  138. static struct dwc2_plat_otg_data meson_gx_dwc2_data;
  139. int board_usb_init(int index, enum usb_init_type init)
  140. {
  141. struct fdtdec_phandle_args args;
  142. const void *blob = gd->fdt_blob;
  143. int node, dwc2_node;
  144. struct udevice *dev, *clk_dev;
  145. struct clk clk;
  146. int ret;
  147. /* find the usb glue node */
  148. node = fdt_node_offset_by_compatible(blob, -1,
  149. "amlogic,meson-gxl-usb-ctrl");
  150. if (node < 0) {
  151. node = fdt_node_offset_by_compatible(blob, -1,
  152. "amlogic,meson-gxm-usb-ctrl");
  153. if (node < 0) {
  154. debug("Not found usb-control node\n");
  155. return -ENODEV;
  156. }
  157. }
  158. if (!fdtdec_get_is_enabled(blob, node)) {
  159. debug("usb is disabled in the device tree\n");
  160. return -ENODEV;
  161. }
  162. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  163. if (ret) {
  164. debug("Not found usb-control device\n");
  165. return ret;
  166. }
  167. /* find the dwc2 node */
  168. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  169. "amlogic,meson-g12a-usb");
  170. if (dwc2_node < 0) {
  171. debug("Not found dwc2 node\n");
  172. return -ENODEV;
  173. }
  174. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  175. debug("dwc2 is disabled in the device tree\n");
  176. return -ENODEV;
  177. }
  178. meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  179. if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  180. debug("usbotg: can't get base address\n");
  181. return -ENODATA;
  182. }
  183. /* Enable clock */
  184. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  185. "#clock-cells", 0, 0, &args);
  186. if (ret) {
  187. debug("usbotg has no clocks defined in the device tree\n");
  188. return ret;
  189. }
  190. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  191. if (ret)
  192. return ret;
  193. if (args.args_count != 1) {
  194. debug("Can't find clock ID in the device tree\n");
  195. return -ENODATA;
  196. }
  197. clk.dev = clk_dev;
  198. clk.id = args.args[0];
  199. ret = clk_enable(&clk);
  200. if (ret) {
  201. debug("Failed to enable usbotg clock\n");
  202. return ret;
  203. }
  204. meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  205. "g-rx-fifo-size", 0);
  206. meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  207. "g-np-tx-fifo-size", 0);
  208. meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  209. "g-tx-fifo-size", 0);
  210. /* Switch to peripheral mode */
  211. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  212. if (ret)
  213. return ret;
  214. return dwc2_udc_probe(&meson_gx_dwc2_data);
  215. }
  216. int board_usb_cleanup(int index, enum usb_init_type init)
  217. {
  218. const void *blob = gd->fdt_blob;
  219. struct udevice *dev;
  220. int node;
  221. int ret;
  222. /* find the usb glue node */
  223. node = fdt_node_offset_by_compatible(blob, -1,
  224. "amlogic,meson-gxl-usb-ctrl");
  225. if (node < 0) {
  226. node = fdt_node_offset_by_compatible(blob, -1,
  227. "amlogic,meson-gxm-usb-ctrl");
  228. if (node < 0) {
  229. debug("Not found usb-control node\n");
  230. return -ENODEV;
  231. }
  232. }
  233. if (!fdtdec_get_is_enabled(blob, node))
  234. return -ENODEV;
  235. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  236. if (ret)
  237. return ret;
  238. /* Switch to OTG mode */
  239. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
  240. if (ret)
  241. return ret;
  242. return 0;
  243. }
  244. #endif