board-g12a.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <asm/arch/boot.h>
  11. #include <asm/arch/eth.h>
  12. #include <asm/arch/g12a.h>
  13. #include <asm/arch/mem.h>
  14. #include <asm/arch/meson-vpu.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <asm/armv8/mmu.h>
  18. #include <linux/sizes.h>
  19. #include <usb.h>
  20. #include <linux/usb/otg.h>
  21. #include <asm/arch/usb.h>
  22. #include <usb/dwc2_udc.h>
  23. #include <phy.h>
  24. #include <clk.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int meson_get_boot_device(void)
  27. {
  28. return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
  29. }
  30. /* Configure the reserved memory zones exported by the secure registers
  31. * into EFI and DTB reserved memory entries.
  32. */
  33. void meson_init_reserved_memory(void *fdt)
  34. {
  35. u64 bl31_size, bl31_start;
  36. u64 bl32_size, bl32_start;
  37. u32 reg;
  38. /*
  39. * Get ARM Trusted Firmware reserved memory zones in :
  40. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  41. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  42. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  43. */
  44. reg = readl(G12A_AO_SEC_GP_CFG3);
  45. bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
  46. >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  47. bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  48. bl31_start = readl(G12A_AO_SEC_GP_CFG5);
  49. bl32_start = readl(G12A_AO_SEC_GP_CFG4);
  50. /* Add BL31 reserved zone */
  51. if (bl31_start && bl31_size)
  52. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  53. /* Add BL32 reserved zone */
  54. if (bl32_start && bl32_size)
  55. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  56. #if defined(CONFIG_VIDEO_MESON)
  57. meson_vpu_rsv_fb(fdt);
  58. #endif
  59. }
  60. phys_size_t get_effective_memsize(void)
  61. {
  62. /* Size is reported in MiB, convert it in bytes */
  63. return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
  64. >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
  65. }
  66. static struct mm_region g12a_mem_map[] = {
  67. {
  68. .virt = 0x0UL,
  69. .phys = 0x0UL,
  70. .size = 0xf5000000UL,
  71. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  72. PTE_BLOCK_INNER_SHARE
  73. }, {
  74. .virt = 0xf5000000UL,
  75. .phys = 0xf5000000UL,
  76. .size = 0x0b000000UL,
  77. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  78. PTE_BLOCK_NON_SHARE |
  79. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  80. }, {
  81. /* List terminator */
  82. 0,
  83. }
  84. };
  85. struct mm_region *mem_map = g12a_mem_map;
  86. static void g12a_enable_external_mdio(void)
  87. {
  88. writel(0x0, ETH_PHY_CNTL2);
  89. }
  90. static void g12a_enable_internal_mdio(void)
  91. {
  92. /* Fire up the PHY PLL */
  93. writel(0x29c0040a, ETH_PLL_CNTL0);
  94. writel(0x927e0000, ETH_PLL_CNTL1);
  95. writel(0xac5f49e5, ETH_PLL_CNTL2);
  96. writel(0x00000000, ETH_PLL_CNTL3);
  97. writel(0x00000000, ETH_PLL_CNTL4);
  98. writel(0x20200000, ETH_PLL_CNTL5);
  99. writel(0x0000c002, ETH_PLL_CNTL6);
  100. writel(0x00000023, ETH_PLL_CNTL7);
  101. writel(0x39c0040a, ETH_PLL_CNTL0);
  102. writel(0x19c0040a, ETH_PLL_CNTL0);
  103. /* Select the internal MDIO */
  104. writel(0x33000180, ETH_PHY_CNTL0);
  105. writel(0x00074043, ETH_PHY_CNTL1);
  106. writel(0x00000260, ETH_PHY_CNTL2);
  107. }
  108. /* Configure the Ethernet MAC with the requested interface mode
  109. * with some optional flags.
  110. */
  111. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  112. {
  113. switch (mode) {
  114. case PHY_INTERFACE_MODE_RGMII:
  115. case PHY_INTERFACE_MODE_RGMII_ID:
  116. case PHY_INTERFACE_MODE_RGMII_RXID:
  117. case PHY_INTERFACE_MODE_RGMII_TXID:
  118. /* Set RGMII mode */
  119. setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
  120. G12A_ETH_REG_0_TX_PHASE(1) |
  121. G12A_ETH_REG_0_TX_RATIO(4) |
  122. G12A_ETH_REG_0_PHY_CLK_EN |
  123. G12A_ETH_REG_0_CLK_EN);
  124. g12a_enable_external_mdio();
  125. break;
  126. case PHY_INTERFACE_MODE_RMII:
  127. /* Set RMII mode */
  128. out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
  129. G12A_ETH_REG_0_INVERT_RMII_CLK |
  130. G12A_ETH_REG_0_CLK_EN);
  131. /* Use G12A RMII Internal PHY */
  132. if (flags & MESON_USE_INTERNAL_RMII_PHY)
  133. g12a_enable_internal_mdio();
  134. else
  135. g12a_enable_external_mdio();
  136. break;
  137. default:
  138. printf("Invalid Ethernet interface mode\n");
  139. return;
  140. }
  141. /* Enable power gate */
  142. clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
  143. }
  144. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
  145. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  146. static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
  147. int board_usb_init(int index, enum usb_init_type init)
  148. {
  149. struct fdtdec_phandle_args args;
  150. const void *blob = gd->fdt_blob;
  151. int node, dwc2_node;
  152. struct udevice *dev, *clk_dev;
  153. struct clk clk;
  154. int ret;
  155. /* find the usb glue node */
  156. node = fdt_node_offset_by_compatible(blob, -1,
  157. "amlogic,meson-g12a-usb-ctrl");
  158. if (node < 0) {
  159. debug("Not found usb-control node\n");
  160. return -ENODEV;
  161. }
  162. if (!fdtdec_get_is_enabled(blob, node)) {
  163. debug("usb is disabled in the device tree\n");
  164. return -ENODEV;
  165. }
  166. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  167. if (ret) {
  168. debug("Not found usb-control device\n");
  169. return ret;
  170. }
  171. /* find the dwc2 node */
  172. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  173. "amlogic,meson-g12a-usb");
  174. if (dwc2_node < 0) {
  175. debug("Not found dwc2 node\n");
  176. return -ENODEV;
  177. }
  178. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  179. debug("dwc2 is disabled in the device tree\n");
  180. return -ENODEV;
  181. }
  182. meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  183. if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  184. debug("usbotg: can't get base address\n");
  185. return -ENODATA;
  186. }
  187. /* Enable clock */
  188. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  189. "#clock-cells", 0, 0, &args);
  190. if (ret) {
  191. debug("usbotg has no clocks defined in the device tree\n");
  192. return ret;
  193. }
  194. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  195. if (ret)
  196. return ret;
  197. if (args.args_count != 1) {
  198. debug("Can't find clock ID in the device tree\n");
  199. return -ENODATA;
  200. }
  201. clk.dev = clk_dev;
  202. clk.id = args.args[0];
  203. ret = clk_enable(&clk);
  204. if (ret) {
  205. debug("Failed to enable usbotg clock\n");
  206. return ret;
  207. }
  208. meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  209. "g-rx-fifo-size", 0);
  210. meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  211. "g-np-tx-fifo-size", 0);
  212. meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  213. "g-tx-fifo-size", 0);
  214. /* Switch to peripheral mode */
  215. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  216. if (ret)
  217. return ret;
  218. return dwc2_udc_probe(&meson_g12a_dwc2_data);
  219. }
  220. int board_usb_cleanup(int index, enum usb_init_type init)
  221. {
  222. const void *blob = gd->fdt_blob;
  223. struct udevice *dev;
  224. int node;
  225. int ret;
  226. /* find the usb glue node */
  227. node = fdt_node_offset_by_compatible(blob, -1,
  228. "amlogic,meson-g12a-usb-ctrl");
  229. if (node < 0)
  230. return -ENODEV;
  231. if (!fdtdec_get_is_enabled(blob, node))
  232. return -ENODEV;
  233. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  234. if (ret)
  235. return ret;
  236. /* Switch to OTG mode */
  237. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
  238. if (ret)
  239. return ret;
  240. return 0;
  241. }
  242. #endif