board-axg.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/axg.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <linux/sizes.h>
  17. #include <usb.h>
  18. #include <linux/usb/otg.h>
  19. #include <asm/arch/usb-gx.h>
  20. #include <usb/dwc2_udc.h>
  21. #include <clk.h>
  22. #include <phy.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int meson_get_boot_device(void)
  25. {
  26. return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
  27. }
  28. /* Configure the reserved memory zones exported by the secure registers
  29. * into EFI and DTB reserved memory entries.
  30. */
  31. void meson_init_reserved_memory(void *fdt)
  32. {
  33. u64 bl31_size, bl31_start;
  34. u64 bl32_size, bl32_start;
  35. u32 reg;
  36. /*
  37. * Get ARM Trusted Firmware reserved memory zones in :
  38. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  39. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  40. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  41. */
  42. reg = readl(AXG_AO_SEC_GP_CFG3);
  43. bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
  44. >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  45. bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  46. bl31_start = readl(AXG_AO_SEC_GP_CFG5);
  47. bl32_start = readl(AXG_AO_SEC_GP_CFG4);
  48. /* Add BL31 reserved zone */
  49. if (bl31_start && bl31_size)
  50. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  51. /* Add BL32 reserved zone */
  52. if (bl32_start && bl32_size)
  53. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  54. }
  55. phys_size_t get_effective_memsize(void)
  56. {
  57. /* Size is reported in MiB, convert it in bytes */
  58. return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
  59. >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
  60. }
  61. static struct mm_region axg_mem_map[] = {
  62. {
  63. .virt = 0x0UL,
  64. .phys = 0x0UL,
  65. .size = 0x80000000UL,
  66. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  67. PTE_BLOCK_INNER_SHARE
  68. }, {
  69. .virt = 0xf0000000UL,
  70. .phys = 0xf0000000UL,
  71. .size = 0x10000000UL,
  72. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  73. PTE_BLOCK_NON_SHARE |
  74. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  75. }, {
  76. /* List terminator */
  77. 0,
  78. }
  79. };
  80. struct mm_region *mem_map = axg_mem_map;
  81. /* Configure the Ethernet MAC with the requested interface mode
  82. * with some optional flags.
  83. */
  84. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  85. {
  86. switch (mode) {
  87. case PHY_INTERFACE_MODE_RGMII:
  88. case PHY_INTERFACE_MODE_RGMII_ID:
  89. case PHY_INTERFACE_MODE_RGMII_RXID:
  90. case PHY_INTERFACE_MODE_RGMII_TXID:
  91. /* Set RGMII mode */
  92. setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  93. AXG_ETH_REG_0_TX_PHASE(1) |
  94. AXG_ETH_REG_0_TX_RATIO(4) |
  95. AXG_ETH_REG_0_PHY_CLK_EN |
  96. AXG_ETH_REG_0_CLK_EN);
  97. break;
  98. case PHY_INTERFACE_MODE_RMII:
  99. /* Set RMII mode */
  100. out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
  101. AXG_ETH_REG_0_INVERT_RMII_CLK |
  102. AXG_ETH_REG_0_CLK_EN);
  103. break;
  104. default:
  105. printf("Invalid Ethernet interface mode\n");
  106. return;
  107. }
  108. /* Enable power gate */
  109. clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
  110. }
  111. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
  112. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  113. static struct dwc2_plat_otg_data meson_gx_dwc2_data;
  114. int board_usb_init(int index, enum usb_init_type init)
  115. {
  116. struct fdtdec_phandle_args args;
  117. const void *blob = gd->fdt_blob;
  118. int node, dwc2_node;
  119. struct udevice *dev, *clk_dev;
  120. struct clk clk;
  121. int ret;
  122. /* find the usb glue node */
  123. node = fdt_node_offset_by_compatible(blob, -1,
  124. "amlogic,meson-gxl-usb-ctrl");
  125. if (node < 0) {
  126. debug("Not found usb-control node\n");
  127. return -ENODEV;
  128. }
  129. if (!fdtdec_get_is_enabled(blob, node)) {
  130. debug("usb is disabled in the device tree\n");
  131. return -ENODEV;
  132. }
  133. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  134. if (ret) {
  135. debug("Not found usb-control device\n");
  136. return ret;
  137. }
  138. /* find the dwc2 node */
  139. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  140. "amlogic,meson-g12a-usb");
  141. if (dwc2_node < 0) {
  142. debug("Not found dwc2 node\n");
  143. return -ENODEV;
  144. }
  145. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  146. debug("dwc2 is disabled in the device tree\n");
  147. return -ENODEV;
  148. }
  149. meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  150. if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  151. debug("usbotg: can't get base address\n");
  152. return -ENODATA;
  153. }
  154. /* Enable clock */
  155. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  156. "#clock-cells", 0, 0, &args);
  157. if (ret) {
  158. debug("usbotg has no clocks defined in the device tree\n");
  159. return ret;
  160. }
  161. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  162. if (ret)
  163. return ret;
  164. if (args.args_count != 1) {
  165. debug("Can't find clock ID in the device tree\n");
  166. return -ENODATA;
  167. }
  168. clk.dev = clk_dev;
  169. clk.id = args.args[0];
  170. ret = clk_enable(&clk);
  171. if (ret) {
  172. debug("Failed to enable usbotg clock\n");
  173. return ret;
  174. }
  175. meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  176. "g-rx-fifo-size", 0);
  177. meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  178. "g-np-tx-fifo-size", 0);
  179. meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  180. "g-tx-fifo-size", 0);
  181. /* Switch to peripheral mode */
  182. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  183. if (ret)
  184. return ret;
  185. return dwc2_udc_probe(&meson_gx_dwc2_data);
  186. }
  187. int board_usb_cleanup(int index, enum usb_init_type init)
  188. {
  189. const void *blob = gd->fdt_blob;
  190. struct udevice *dev;
  191. int node;
  192. int ret;
  193. /* find the usb glue node */
  194. node = fdt_node_offset_by_compatible(blob, -1,
  195. "amlogic,meson-gxl-usb-ctrl");
  196. if (node < 0) {
  197. debug("Not found usb-control node\n");
  198. return -ENODEV;
  199. }
  200. if (!fdtdec_get_is_enabled(blob, node))
  201. return -ENODEV;
  202. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  203. if (ret)
  204. return ret;
  205. /* Switch to OTG mode */
  206. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
  207. if (ret)
  208. return ret;
  209. return 0;
  210. }
  211. #endif