init.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Copyright (C) 2019 BayLibre, SAS
  5. * Author: Fabien Parent <fparent@baylibre.com>
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <init.h>
  13. #include <ram.h>
  14. #include <asm/arch/misc.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <asm/cache.h>
  17. #include <asm/global_data.h>
  18. #include <asm/sections.h>
  19. #include <dm/uclass.h>
  20. #include <dt-bindings/clock/mt8516-clk.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int dram_init(void)
  23. {
  24. int ret;
  25. ret = fdtdec_setup_memory_banksize();
  26. if (ret)
  27. return ret;
  28. return fdtdec_setup_mem_size_base();
  29. }
  30. int dram_init_banksize(void)
  31. {
  32. gd->bd->bi_dram[0].start = gd->ram_base;
  33. gd->bd->bi_dram[0].size = gd->ram_size;
  34. return 0;
  35. }
  36. int mtk_pll_early_init(void)
  37. {
  38. unsigned long pll_rates[] = {
  39. [CLK_APMIXED_ARMPLL] = 1300000000,
  40. [CLK_APMIXED_MAINPLL] = 1501000000,
  41. [CLK_APMIXED_UNIVPLL] = 1248000000,
  42. [CLK_APMIXED_MMPLL] = 380000000,
  43. };
  44. struct udevice *dev;
  45. int ret, i;
  46. ret = uclass_get_device_by_driver(UCLASS_CLK,
  47. DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
  48. if (ret)
  49. return ret;
  50. /* configure default rate then enable apmixedsys */
  51. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  52. struct clk clk = { .id = i, .dev = dev };
  53. ret = clk_set_rate(&clk, pll_rates[i]);
  54. if (ret)
  55. return ret;
  56. ret = clk_enable(&clk);
  57. if (ret)
  58. return ret;
  59. }
  60. return 0;
  61. }
  62. int mtk_soc_early_init(void)
  63. {
  64. int ret;
  65. /* initialize early clocks */
  66. ret = mtk_pll_early_init();
  67. if (ret)
  68. return ret;
  69. return 0;
  70. }
  71. void reset_cpu(ulong addr)
  72. {
  73. psci_system_reset();
  74. }
  75. int print_cpuinfo(void)
  76. {
  77. printf("CPU: MediaTek MT8516\n");
  78. return 0;
  79. }
  80. static struct mm_region mt8516_mem_map[] = {
  81. {
  82. /* DDR */
  83. .virt = 0x40000000UL,
  84. .phys = 0x40000000UL,
  85. .size = 0x20000000UL,
  86. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  87. }, {
  88. .virt = 0x00000000UL,
  89. .phys = 0x00000000UL,
  90. .size = 0x20000000UL,
  91. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  92. PTE_BLOCK_NON_SHARE |
  93. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  94. }, {
  95. 0,
  96. }
  97. };
  98. struct mm_region *mem_map = mt8516_mem_map;