init.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Configuration for MediaTek MT8512 SoC
  4. *
  5. * Copyright (C) 2019 MediaTek Inc.
  6. * Author: Mingming Lee <mingming.lee@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <ram.h>
  15. #include <wdt.h>
  16. #include <asm/arch/misc.h>
  17. #include <asm/armv8/mmu.h>
  18. #include <asm/cache.h>
  19. #include <asm/global_data.h>
  20. #include <asm/sections.h>
  21. #include <dm/uclass.h>
  22. #include <dt-bindings/clock/mt8512-clk.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int dram_init(void)
  25. {
  26. return fdtdec_setup_mem_size_base();
  27. }
  28. phys_size_t get_effective_memsize(void)
  29. {
  30. /* limit stack below tee reserve memory */
  31. return gd->ram_size - 6 * SZ_1M;
  32. }
  33. int dram_init_banksize(void)
  34. {
  35. gd->bd->bi_dram[0].start = gd->ram_base;
  36. gd->bd->bi_dram[0].size = get_effective_memsize();
  37. return 0;
  38. }
  39. void reset_cpu(ulong addr)
  40. {
  41. struct udevice *watchdog_dev = NULL;
  42. if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
  43. if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
  44. psci_system_reset();
  45. wdt_expire_now(watchdog_dev, 0);
  46. }
  47. int print_cpuinfo(void)
  48. {
  49. debug("CPU: MediaTek MT8512\n");
  50. return 0;
  51. }
  52. static struct mm_region mt8512_mem_map[] = {
  53. {
  54. /* DDR */
  55. .virt = 0x40000000UL,
  56. .phys = 0x40000000UL,
  57. .size = 0x40000000UL,
  58. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  59. }, {
  60. .virt = 0x00000000UL,
  61. .phys = 0x00000000UL,
  62. .size = 0x40000000UL,
  63. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  64. PTE_BLOCK_NON_SHARE |
  65. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  66. }, {
  67. 0,
  68. }
  69. };
  70. struct mm_region *mem_map = mt8512_mem_map;