init.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <asm/arch/misc.h>
  14. #include <asm/global_data.h>
  15. #include <asm/sections.h>
  16. #include <dm/uclass.h>
  17. #include <linux/bitops.h>
  18. #include <linux/io.h>
  19. #include <dt-bindings/clock/mt7629-clk.h>
  20. #define L2_CFG_BASE 0x10200000
  21. #define L2_CFG_SIZE 0x1000
  22. #define L2_SHARE_CFG_MP0 0x7f0
  23. #define L2_SHARE_MODE_OFF BIT(8)
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int mtk_pll_early_init(void)
  26. {
  27. unsigned long pll_rates[] = {
  28. [CLK_APMIXED_ARMPLL] = 1250000000,
  29. [CLK_APMIXED_MAINPLL] = 1120000000,
  30. [CLK_APMIXED_UNIV2PLL] = 1200000000,
  31. [CLK_APMIXED_ETH1PLL] = 500000000,
  32. [CLK_APMIXED_ETH2PLL] = 700000000,
  33. [CLK_APMIXED_SGMIPLL] = 650000000,
  34. };
  35. struct udevice *dev;
  36. int ret, i;
  37. ret = uclass_get_device_by_driver(UCLASS_CLK,
  38. DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
  39. if (ret)
  40. return ret;
  41. /* configure default rate then enable apmixedsys */
  42. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  43. struct clk clk = { .id = i, .dev = dev };
  44. ret = clk_set_rate(&clk, pll_rates[i]);
  45. if (ret)
  46. return ret;
  47. ret = clk_enable(&clk);
  48. if (ret)
  49. return ret;
  50. }
  51. /* setup mcu bus */
  52. ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  53. DM_DRIVER_GET(mtk_mcucfg), &dev);
  54. if (ret)
  55. return ret;
  56. return 0;
  57. }
  58. int mtk_soc_early_init(void)
  59. {
  60. struct udevice *dev;
  61. int ret;
  62. /* initialize early clocks */
  63. ret = mtk_pll_early_init();
  64. if (ret)
  65. return ret;
  66. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  67. if (ret)
  68. return ret;
  69. return 0;
  70. }
  71. int mach_cpu_init(void)
  72. {
  73. void __iomem *base;
  74. base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
  75. /* disable L2C shared mode */
  76. writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
  77. return 0;
  78. }
  79. int dram_init(void)
  80. {
  81. struct ram_info ram;
  82. struct udevice *dev;
  83. int ret;
  84. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  85. if (ret)
  86. return ret;
  87. ret = ram_get_info(dev, &ram);
  88. if (ret)
  89. return ret;
  90. debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
  91. gd->ram_size = ram.size;
  92. return 0;
  93. }
  94. int print_cpuinfo(void)
  95. {
  96. void __iomem *chipid;
  97. u32 hwcode, swver;
  98. chipid = ioremap(VER_BASE, VER_SIZE);
  99. hwcode = readl(chipid + APHW_CODE);
  100. swver = readl(chipid + APSW_VER);
  101. printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
  102. return 0;
  103. }