common.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: Common Architecture initialization
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include <asm/global_data.h>
  15. #include "common.h"
  16. #include <dm.h>
  17. #include <remoteproc.h>
  18. #include <asm/cache.h>
  19. #include <linux/soc/ti/ti_sci_protocol.h>
  20. #include <fdt_support.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/hardware.h>
  23. #include <asm/io.h>
  24. #include <fs_loader.h>
  25. #include <fs.h>
  26. #include <env.h>
  27. #include <elf.h>
  28. #include <soc.h>
  29. struct ti_sci_handle *get_ti_sci_handle(void)
  30. {
  31. struct udevice *dev;
  32. int ret;
  33. ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
  34. DM_DRIVER_GET(ti_sci), &dev);
  35. if (ret)
  36. panic("Failed to get SYSFW (%d)\n", ret);
  37. return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
  38. }
  39. void k3_sysfw_print_ver(void)
  40. {
  41. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  42. char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
  43. /*
  44. * Output System Firmware version info. Note that since the
  45. * 'firmware_description' field is not guaranteed to be zero-
  46. * terminated we manually add a \0 terminator if needed. Further
  47. * note that we intentionally no longer rely on the extended
  48. * printf() formatter '%.*s' to not having to require a more
  49. * full-featured printf() implementation.
  50. */
  51. strncpy(fw_desc, ti_sci->version.firmware_description,
  52. sizeof(ti_sci->version.firmware_description));
  53. fw_desc[sizeof(fw_desc) - 1] = '\0';
  54. printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
  55. ti_sci->version.abi_major, ti_sci->version.abi_minor,
  56. ti_sci->version.firmware_revision, fw_desc);
  57. }
  58. void mmr_unlock(phys_addr_t base, u32 partition)
  59. {
  60. /* Translate the base address */
  61. phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  62. /* Unlock the requested partition if locked using two-step sequence */
  63. writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  64. writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  65. }
  66. bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
  67. {
  68. if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
  69. return false;
  70. return data->num_components > 1;
  71. }
  72. DECLARE_GLOBAL_DATA_PTR;
  73. #ifdef CONFIG_K3_EARLY_CONS
  74. int early_console_init(void)
  75. {
  76. struct udevice *dev;
  77. int ret;
  78. gd->baudrate = CONFIG_BAUDRATE;
  79. ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
  80. &dev);
  81. if (ret) {
  82. printf("Error getting serial dev for early console! (%d)\n",
  83. ret);
  84. return ret;
  85. }
  86. gd->cur_serial_dev = dev;
  87. gd->flags |= GD_FLG_SERIAL_READY;
  88. gd->have_console = 1;
  89. return 0;
  90. }
  91. #endif
  92. #ifdef CONFIG_SYS_K3_SPL_ATF
  93. void init_env(void)
  94. {
  95. #ifdef CONFIG_SPL_ENV_SUPPORT
  96. char *part;
  97. env_init();
  98. env_relocate();
  99. switch (spl_boot_device()) {
  100. case BOOT_DEVICE_MMC2:
  101. part = env_get("bootpart");
  102. env_set("storage_interface", "mmc");
  103. env_set("fw_dev_part", part);
  104. break;
  105. case BOOT_DEVICE_SPI:
  106. env_set("storage_interface", "ubi");
  107. env_set("fw_ubi_mtdpart", "UBI");
  108. env_set("fw_ubi_volume", "UBI0");
  109. break;
  110. default:
  111. printf("%s from device %u not supported!\n",
  112. __func__, spl_boot_device());
  113. return;
  114. }
  115. #endif
  116. }
  117. #ifdef CONFIG_FS_LOADER
  118. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  119. {
  120. struct udevice *fsdev;
  121. char *name = NULL;
  122. int size = 0;
  123. *loadaddr = 0;
  124. #ifdef CONFIG_SPL_ENV_SUPPORT
  125. switch (spl_boot_device()) {
  126. case BOOT_DEVICE_MMC2:
  127. name = env_get(name_fw);
  128. *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
  129. break;
  130. default:
  131. printf("Loading rproc fw image from device %u not supported!\n",
  132. spl_boot_device());
  133. return 0;
  134. }
  135. #endif
  136. if (!*loadaddr)
  137. return 0;
  138. if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
  139. size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
  140. 0, 0);
  141. }
  142. return size;
  143. }
  144. #else
  145. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  146. {
  147. return 0;
  148. }
  149. #endif
  150. __weak void start_non_linux_remote_cores(void)
  151. {
  152. }
  153. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  154. {
  155. typedef void __noreturn (*image_entry_noargs_t)(void);
  156. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  157. u32 loadaddr = 0;
  158. int ret, size;
  159. /* Release all the exclusive devices held by SPL before starting ATF */
  160. ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
  161. ret = rproc_init();
  162. if (ret)
  163. panic("rproc failed to be initialized (%d)\n", ret);
  164. init_env();
  165. start_non_linux_remote_cores();
  166. size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
  167. &loadaddr);
  168. /*
  169. * It is assumed that remoteproc device 1 is the corresponding
  170. * Cortex-A core which runs ATF. Make sure DT reflects the same.
  171. */
  172. ret = rproc_load(1, spl_image->entry_point, 0x200);
  173. if (ret)
  174. panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
  175. /* Add an extra newline to differentiate the ATF logs from SPL */
  176. printf("Starting ATF on ARM64 core...\n\n");
  177. ret = rproc_start(1);
  178. if (ret)
  179. panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
  180. if (!(size > 0 && valid_elf_image(loadaddr))) {
  181. debug("Shutting down...\n");
  182. release_resources_for_core_shutdown();
  183. while (1)
  184. asm volatile("wfe");
  185. }
  186. image_entry_noargs_t image_entry =
  187. (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
  188. image_entry();
  189. }
  190. #endif
  191. #if defined(CONFIG_OF_LIBFDT)
  192. int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
  193. {
  194. u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
  195. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  196. int ret, node, subnode, len, prev_node;
  197. u32 range[4], addr, size;
  198. const fdt32_t *sub_reg;
  199. ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
  200. msmc_size = msmc_end - msmc_start + 1;
  201. debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
  202. msmc_start, msmc_size);
  203. /* find or create "msmc_sram node */
  204. ret = fdt_path_offset(blob, parent_path);
  205. if (ret < 0)
  206. return ret;
  207. node = fdt_find_or_add_subnode(blob, ret, node_name);
  208. if (node < 0)
  209. return node;
  210. ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
  211. if (ret < 0)
  212. return ret;
  213. reg[0] = cpu_to_fdt64(msmc_start);
  214. reg[1] = cpu_to_fdt64(msmc_size);
  215. ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
  216. if (ret < 0)
  217. return ret;
  218. fdt_setprop_cell(blob, node, "#address-cells", 1);
  219. fdt_setprop_cell(blob, node, "#size-cells", 1);
  220. range[0] = 0;
  221. range[1] = cpu_to_fdt32(msmc_start >> 32);
  222. range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
  223. range[3] = cpu_to_fdt32(msmc_size);
  224. ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
  225. if (ret < 0)
  226. return ret;
  227. subnode = fdt_first_subnode(blob, node);
  228. prev_node = 0;
  229. /* Look for invalid subnodes and delete them */
  230. while (subnode >= 0) {
  231. sub_reg = fdt_getprop(blob, subnode, "reg", &len);
  232. addr = fdt_read_number(sub_reg, 1);
  233. sub_reg++;
  234. size = fdt_read_number(sub_reg, 1);
  235. debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
  236. subnode, addr, size);
  237. if (addr + size > msmc_size ||
  238. !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
  239. !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
  240. fdt_del_node(blob, subnode);
  241. debug("%s: deleting subnode %d\n", __func__, subnode);
  242. if (!prev_node)
  243. subnode = fdt_first_subnode(blob, node);
  244. else
  245. subnode = fdt_next_subnode(blob, prev_node);
  246. } else {
  247. prev_node = subnode;
  248. subnode = fdt_next_subnode(blob, prev_node);
  249. }
  250. }
  251. return 0;
  252. }
  253. int fdt_disable_node(void *blob, char *node_path)
  254. {
  255. int offs;
  256. int ret;
  257. offs = fdt_path_offset(blob, node_path);
  258. if (offs < 0) {
  259. printf("Node %s not found.\n", node_path);
  260. return offs;
  261. }
  262. ret = fdt_setprop_string(blob, offs, "status", "disabled");
  263. if (ret < 0) {
  264. printf("Could not add status property to node %s: %s\n",
  265. node_path, fdt_strerror(ret));
  266. return ret;
  267. }
  268. return 0;
  269. }
  270. #endif
  271. #ifndef CONFIG_SYSRESET
  272. void reset_cpu(ulong ignored)
  273. {
  274. }
  275. #endif
  276. #if defined(CONFIG_DISPLAY_CPUINFO)
  277. int print_cpuinfo(void)
  278. {
  279. struct udevice *soc;
  280. char name[64];
  281. int ret;
  282. printf("SoC: ");
  283. ret = soc_get(&soc);
  284. if (ret) {
  285. printf("UNKNOWN\n");
  286. return 0;
  287. }
  288. ret = soc_get_family(soc, name, 64);
  289. if (!ret) {
  290. printf("%s ", name);
  291. }
  292. ret = soc_get_revision(soc, name, 64);
  293. if (!ret) {
  294. printf("%s\n", name);
  295. }
  296. return 0;
  297. }
  298. #endif
  299. bool soc_is_j721e(void)
  300. {
  301. u32 soc;
  302. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  303. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  304. return soc == J721E;
  305. }
  306. bool soc_is_j7200(void)
  307. {
  308. u32 soc;
  309. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  310. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  311. return soc == J7200;
  312. }
  313. #ifdef CONFIG_ARM64
  314. void board_prep_linux(bootm_headers_t *images)
  315. {
  316. debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
  317. images->os.start, images->os.end);
  318. __asm_flush_dcache_range(images->os.start,
  319. ROUND(images->os.end,
  320. CONFIG_SYS_CACHELINE_SIZE));
  321. }
  322. #endif
  323. #ifdef CONFIG_CPU_V7R
  324. void disable_linefill_optimization(void)
  325. {
  326. u32 actlr;
  327. /*
  328. * On K3 devices there are 2 conditions where R5F can deadlock:
  329. * 1.When software is performing series of store operations to
  330. * cacheable write back/write allocate memory region and later
  331. * on software execute barrier operation (DSB or DMB). R5F may
  332. * hang at the barrier instruction.
  333. * 2.When software is performing a mix of load and store operations
  334. * within a tight loop and store operations are all writing to
  335. * cacheable write back/write allocates memory regions, R5F may
  336. * hang at one of the load instruction.
  337. *
  338. * To avoid the above two conditions disable linefill optimization
  339. * inside Cortex R5F.
  340. */
  341. asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
  342. actlr |= (1 << 13); /* Set DLFO bit */
  343. asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
  344. }
  345. #endif
  346. void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
  347. {
  348. struct ti_sci_msg_fwl_region region;
  349. struct ti_sci_fwl_ops *fwl_ops;
  350. struct ti_sci_handle *ti_sci;
  351. size_t i, j;
  352. ti_sci = get_ti_sci_handle();
  353. fwl_ops = &ti_sci->ops.fwl_ops;
  354. for (i = 0; i < fwl_data_size; i++) {
  355. for (j = 0; j < fwl_data[i].regions; j++) {
  356. region.fwl_id = fwl_data[i].fwl_id;
  357. region.region = j;
  358. region.n_permission_regs = 3;
  359. fwl_ops->get_fwl_region(ti_sci, &region);
  360. if (region.control != 0) {
  361. pr_debug("Attempting to disable firewall %5d (%25s)\n",
  362. region.fwl_id, fwl_data[i].name);
  363. region.control = 0;
  364. if (fwl_ops->set_fwl_region(ti_sci, &region))
  365. pr_err("Could not disable firewall %5d (%25s)\n",
  366. region.fwl_id, fwl_data[i].name);
  367. }
  368. }
  369. }
  370. }
  371. void spl_enable_dcache(void)
  372. {
  373. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  374. phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
  375. dram_init_banksize();
  376. /* reserve TLB table */
  377. gd->arch.tlb_size = PGTABLE_SIZE;
  378. ram_top += get_effective_memsize();
  379. /* keep ram_top in the 32-bit address space */
  380. if (ram_top >= 0x100000000)
  381. ram_top = (phys_addr_t) 0x100000000;
  382. gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
  383. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  384. gd->arch.tlb_addr + gd->arch.tlb_size);
  385. dcache_enable();
  386. #endif
  387. }
  388. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  389. void spl_board_prepare_for_boot(void)
  390. {
  391. dcache_disable();
  392. }
  393. void spl_board_prepare_for_linux(void)
  394. {
  395. dcache_disable();
  396. }
  397. #endif