am6_init.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * AM6: SoC specific initialization
  4. *
  5. * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <fdt_support.h>
  10. #include <init.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <spl.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/sysfw-loader.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include "common.h"
  18. #include <dm.h>
  19. #include <dm/uclass-internal.h>
  20. #include <dm/pinctrl.h>
  21. #include <linux/soc/ti/ti_sci_protocol.h>
  22. #include <log.h>
  23. #include <mmc.h>
  24. #include <stdlib.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifdef CONFIG_SPL_BUILD
  27. #ifdef CONFIG_K3_LOAD_SYSFW
  28. #ifdef CONFIG_TI_SECURE_DEVICE
  29. struct fwl_data main_cbass_fwls[] = {
  30. { "MMCSD1_CFG", 2057, 1 },
  31. { "MMCSD0_CFG", 2058, 1 },
  32. { "USB3SS0_SLV0", 2176, 2 },
  33. { "PCIE0_SLV", 2336, 8 },
  34. { "PCIE1_SLV", 2337, 8 },
  35. { "PCIE0_CFG", 2688, 1 },
  36. { "PCIE1_CFG", 2689, 1 },
  37. }, mcu_cbass_fwls[] = {
  38. { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  39. { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  40. { "MCU_FSS0_S1", 1033, 8 },
  41. { "MCU_FSS0_S0", 1036, 8 },
  42. { "MCU_CPSW0", 1220, 1 },
  43. };
  44. #endif
  45. #endif
  46. static void ctrl_mmr_unlock(void)
  47. {
  48. /* Unlock all WKUP_CTRL_MMR0 module registers */
  49. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  50. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  51. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  52. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  53. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  54. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  55. /* Unlock all MCU_CTRL_MMR0 module registers */
  56. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  57. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  58. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  59. mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  60. /* Unlock all CTRL_MMR0 module registers */
  61. mmr_unlock(CTRL_MMR0_BASE, 0);
  62. mmr_unlock(CTRL_MMR0_BASE, 1);
  63. mmr_unlock(CTRL_MMR0_BASE, 2);
  64. mmr_unlock(CTRL_MMR0_BASE, 3);
  65. mmr_unlock(CTRL_MMR0_BASE, 6);
  66. mmr_unlock(CTRL_MMR0_BASE, 7);
  67. }
  68. /*
  69. * This uninitialized global variable would normal end up in the .bss section,
  70. * but the .bss is cleared between writing and reading this variable, so move
  71. * it to the .data section.
  72. */
  73. u32 bootindex __attribute__((section(".data")));
  74. static void store_boot_index_from_rom(void)
  75. {
  76. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  77. }
  78. #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
  79. void k3_mmc_stop_clock(void)
  80. {
  81. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  82. struct mmc *mmc = find_mmc_device(0);
  83. if (!mmc)
  84. return;
  85. mmc->saved_clock = mmc->clock;
  86. mmc_set_clock(mmc, 0, true);
  87. }
  88. }
  89. void k3_mmc_restart_clock(void)
  90. {
  91. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  92. struct mmc *mmc = find_mmc_device(0);
  93. if (!mmc)
  94. return;
  95. mmc_set_clock(mmc, mmc->saved_clock, false);
  96. }
  97. }
  98. #else
  99. void k3_mmc_stop_clock(void) {}
  100. void k3_mmc_restart_clock(void) {}
  101. #endif
  102. #if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
  103. #define CTRLMMR_SERDES0_CTRL 0x00104080
  104. #define PCIE_LANE0 0x1
  105. static int fixup_usb_boot(void)
  106. {
  107. int ret;
  108. switch (spl_boot_device()) {
  109. case BOOT_DEVICE_USB:
  110. /*
  111. * If bootmode is Host bootmode, fixup the dr_mode to host
  112. * before the dwc3 bind takes place
  113. */
  114. ret = fdt_find_and_setprop((void *)gd->fdt_blob,
  115. "/interconnect@100000/dwc3@4000000/usb@10000",
  116. "dr_mode", "host", 11, 0);
  117. if (ret)
  118. printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
  119. ret);
  120. fallthrough;
  121. case BOOT_DEVICE_DFU:
  122. /*
  123. * The serdes mux between PCIe and USB3 needs to be set to PCIe for
  124. * accessing the interface at USB 2.0
  125. */
  126. writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
  127. default:
  128. break;
  129. }
  130. return 0;
  131. }
  132. int fdtdec_board_setup(const void *fdt_blob)
  133. {
  134. return fixup_usb_boot();
  135. }
  136. #endif
  137. void board_init_f(ulong dummy)
  138. {
  139. #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  140. struct udevice *dev;
  141. size_t pool_size;
  142. void *pool_addr;
  143. int ret;
  144. #endif
  145. /*
  146. * Cannot delay this further as there is a chance that
  147. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  148. */
  149. store_boot_index_from_rom();
  150. /* Make all control module registers accessible */
  151. ctrl_mmr_unlock();
  152. #ifdef CONFIG_CPU_V7R
  153. disable_linefill_optimization();
  154. setup_k3_mpu_regions();
  155. #endif
  156. /* Init DM early in-order to invoke system controller */
  157. spl_early_init();
  158. #ifdef CONFIG_K3_EARLY_CONS
  159. /*
  160. * Allow establishing an early console as required for example when
  161. * doing a UART-based boot. Note that this console may not "survive"
  162. * through a SYSFW PM-init step and will need a re-init in some way
  163. * due to changing module clock frequencies.
  164. */
  165. early_console_init();
  166. #endif
  167. #ifdef CONFIG_K3_LOAD_SYSFW
  168. /*
  169. * Initialize an early full malloc environment. Do so by allocating a
  170. * new malloc area inside the currently active pre-relocation "first"
  171. * malloc pool of which we use all that's left.
  172. */
  173. pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
  174. pool_addr = malloc(pool_size);
  175. if (!pool_addr)
  176. panic("ERROR: Can't allocate full malloc pool!\n");
  177. mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
  178. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  179. debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
  180. __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
  181. /*
  182. * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  183. * regardless of the result of pinctrl. Do this without probing the
  184. * device, but instead by searching the device that would request the
  185. * given sequence number if probed. The UART will be used by the system
  186. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  187. * to initialize its pin settings.
  188. */
  189. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
  190. if (!ret)
  191. pinctrl_select_state(dev, "default");
  192. /*
  193. * Load, start up, and configure system controller firmware while
  194. * also populating the SYSFW post-PM configuration callback hook.
  195. */
  196. k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
  197. /* Prepare console output */
  198. preloader_console_init();
  199. /* Disable ROM configured firewalls right after loading sysfw */
  200. #ifdef CONFIG_TI_SECURE_DEVICE
  201. remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
  202. remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
  203. #endif
  204. #else
  205. /* Prepare console output */
  206. preloader_console_init();
  207. #endif
  208. /* Output System Firmware version info */
  209. k3_sysfw_print_ver();
  210. /* Perform EEPROM-based board detection */
  211. do_board_detect();
  212. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  213. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
  214. &dev);
  215. if (ret)
  216. printf("AVS init failed: %d\n", ret);
  217. #endif
  218. #ifdef CONFIG_K3_AM654_DDRSS
  219. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  220. if (ret)
  221. panic("DRAM init failed: %d\n", ret);
  222. #endif
  223. spl_enable_dcache();
  224. }
  225. u32 spl_mmc_boot_mode(const u32 boot_device)
  226. {
  227. #if defined(CONFIG_SUPPORT_EMMC_BOOT)
  228. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  229. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  230. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  231. /* eMMC boot0 mode is only supported for primary boot */
  232. if (bootindex == K3_PRIMARY_BOOTMODE &&
  233. bootmode == BOOT_DEVICE_MMC1)
  234. return MMCSD_MODE_EMMCBOOT;
  235. #endif
  236. /* Everything else use filesystem if available */
  237. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  238. return MMCSD_MODE_FS;
  239. #else
  240. return MMCSD_MODE_RAW;
  241. #endif
  242. }
  243. static u32 __get_backup_bootmedia(u32 devstat)
  244. {
  245. u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  246. CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  247. switch (bkup_boot) {
  248. case BACKUP_BOOT_DEVICE_USB:
  249. return BOOT_DEVICE_USB;
  250. case BACKUP_BOOT_DEVICE_UART:
  251. return BOOT_DEVICE_UART;
  252. case BACKUP_BOOT_DEVICE_ETHERNET:
  253. return BOOT_DEVICE_ETHERNET;
  254. case BACKUP_BOOT_DEVICE_MMC2:
  255. {
  256. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  257. CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  258. if (port == 0x0)
  259. return BOOT_DEVICE_MMC1;
  260. return BOOT_DEVICE_MMC2;
  261. }
  262. case BACKUP_BOOT_DEVICE_SPI:
  263. return BOOT_DEVICE_SPI;
  264. case BACKUP_BOOT_DEVICE_HYPERFLASH:
  265. return BOOT_DEVICE_HYPERFLASH;
  266. case BACKUP_BOOT_DEVICE_I2C:
  267. return BOOT_DEVICE_I2C;
  268. };
  269. return BOOT_DEVICE_RAM;
  270. }
  271. static u32 __get_primary_bootmedia(u32 devstat)
  272. {
  273. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  274. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  275. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  276. bootmode = BOOT_DEVICE_SPI;
  277. if (bootmode == BOOT_DEVICE_MMC2) {
  278. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
  279. CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
  280. if (port == 0x0)
  281. bootmode = BOOT_DEVICE_MMC1;
  282. } else if (bootmode == BOOT_DEVICE_MMC1) {
  283. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
  284. CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
  285. if (port == 0x1)
  286. bootmode = BOOT_DEVICE_MMC2;
  287. } else if (bootmode == BOOT_DEVICE_DFU) {
  288. u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
  289. CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
  290. if (mode == 0x2)
  291. bootmode = BOOT_DEVICE_USB;
  292. }
  293. return bootmode;
  294. }
  295. u32 spl_boot_device(void)
  296. {
  297. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  298. if (bootindex == K3_PRIMARY_BOOTMODE)
  299. return __get_primary_bootmedia(devstat);
  300. else
  301. return __get_backup_bootmedia(devstat);
  302. }
  303. #endif
  304. #ifdef CONFIG_SYS_K3_SPL_ATF
  305. #define AM6_DEV_MCU_RTI0 134
  306. #define AM6_DEV_MCU_RTI1 135
  307. #define AM6_DEV_MCU_ARMSS0_CPU0 159
  308. #define AM6_DEV_MCU_ARMSS0_CPU1 245
  309. void release_resources_for_core_shutdown(void)
  310. {
  311. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  312. struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
  313. struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
  314. int ret;
  315. u32 i;
  316. const u32 put_device_ids[] = {
  317. AM6_DEV_MCU_RTI0,
  318. AM6_DEV_MCU_RTI1,
  319. };
  320. /* Iterate through list of devices to put (shutdown) */
  321. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  322. u32 id = put_device_ids[i];
  323. ret = dev_ops->put_device(ti_sci, id);
  324. if (ret)
  325. panic("Failed to put device %u (%d)\n", id, ret);
  326. }
  327. const u32 put_core_ids[] = {
  328. AM6_DEV_MCU_ARMSS0_CPU1,
  329. AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  330. };
  331. /* Iterate through list of cores to put (shutdown) */
  332. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  333. u32 id = put_core_ids[i];
  334. /*
  335. * Queue up the core shutdown request. Note that this call
  336. * needs to be followed up by an actual invocation of an WFE
  337. * or WFI CPU instruction.
  338. */
  339. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  340. if (ret)
  341. panic("Failed sending core %u shutdown message (%d)\n",
  342. id, ret);
  343. }
  344. }
  345. #endif