timer.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <div64.h>
  13. #include <asm/global_data.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. /* General purpose timers registers */
  18. struct mxc_gpt {
  19. unsigned int control;
  20. unsigned int prescaler;
  21. unsigned int status;
  22. unsigned int nouse[6];
  23. unsigned int counter;
  24. };
  25. static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
  26. /* General purpose timers bitfields */
  27. #define GPTCR_SWR (1 << 15) /* Software reset */
  28. #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
  29. #define GPTCR_FRR (1 << 9) /* Freerun / restart */
  30. #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
  31. #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
  32. #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
  33. #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
  34. #define GPTCR_TEN 1 /* Timer enable */
  35. #define GPTPR_PRESCALER24M_SHIFT 12
  36. #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static inline int gpt_has_clk_source_osc(void)
  39. {
  40. if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
  41. is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
  42. is_mx6ull() || is_mx6sll() || is_mx7())
  43. return 1;
  44. return 0;
  45. }
  46. static inline ulong gpt_get_clk(void)
  47. {
  48. #ifdef CONFIG_MXC_GPT_HCLK
  49. if (gpt_has_clk_source_osc())
  50. return MXC_HCLK >> 3;
  51. else
  52. return mxc_get_clock(MXC_IPG_PERCLK);
  53. #else
  54. return MXC_CLK32;
  55. #endif
  56. }
  57. int timer_init(void)
  58. {
  59. int i;
  60. /* setup GP Timer 1 */
  61. __raw_writel(GPTCR_SWR, &cur_gpt->control);
  62. /* We have no udelay by now */
  63. for (i = 0; i < 100; i++)
  64. __raw_writel(0, &cur_gpt->control);
  65. i = __raw_readl(&cur_gpt->control);
  66. i &= ~GPTCR_CLKSOURCE_MASK;
  67. #ifdef CONFIG_MXC_GPT_HCLK
  68. if (gpt_has_clk_source_osc()) {
  69. i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
  70. /*
  71. * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
  72. * Enable bit and prescaler
  73. */
  74. if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
  75. is_mx6sll() || is_mx7()) {
  76. i |= GPTCR_24MEN;
  77. /* Produce 3Mhz clock */
  78. __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
  79. &cur_gpt->prescaler);
  80. }
  81. } else {
  82. i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
  83. }
  84. #else
  85. __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  86. i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
  87. #endif
  88. __raw_writel(i, &cur_gpt->control);
  89. gd->arch.tbl = __raw_readl(&cur_gpt->counter);
  90. gd->arch.tbu = 0;
  91. return 0;
  92. }
  93. unsigned long timer_read_counter(void)
  94. {
  95. return __raw_readl(&cur_gpt->counter); /* current tick value */
  96. }
  97. /*
  98. * This function is derived from PowerPC code (timebase clock frequency).
  99. * On ARM it returns the number of timer ticks per second.
  100. */
  101. ulong get_tbclk(void)
  102. {
  103. return gpt_get_clk();
  104. }
  105. /*
  106. * This function is intended for SHORT delays only.
  107. * It will overflow at around 10 seconds @ 400MHz,
  108. * or 20 seconds @ 200MHz.
  109. */
  110. unsigned long usec2ticks(unsigned long _usec)
  111. {
  112. unsigned long long usec = _usec;
  113. usec *= get_tbclk();
  114. usec += 999999;
  115. do_div(usec, 1000000);
  116. return usec;
  117. }