clock.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <command.h>
  8. #include <div64.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <errno.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/sys_proto.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. int get_clocks(void)
  16. {
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
  19. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  20. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
  21. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  22. #endif
  23. #endif
  24. return 0;
  25. }
  26. static u32 get_fast_plat_clk(void)
  27. {
  28. return scg_clk_get_rate(SCG_NIC0_CLK);
  29. }
  30. static u32 get_slow_plat_clk(void)
  31. {
  32. return scg_clk_get_rate(SCG_NIC1_CLK);
  33. }
  34. static u32 get_ipg_clk(void)
  35. {
  36. return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
  37. }
  38. u32 get_lpuart_clk(void)
  39. {
  40. int index = 0;
  41. const u32 lpuart_array[] = {
  42. LPUART0_RBASE,
  43. LPUART1_RBASE,
  44. LPUART2_RBASE,
  45. LPUART3_RBASE,
  46. LPUART4_RBASE,
  47. LPUART5_RBASE,
  48. LPUART6_RBASE,
  49. LPUART7_RBASE,
  50. };
  51. const enum pcc_clk lpuart_pcc_clks[] = {
  52. PER_CLK_LPUART4,
  53. PER_CLK_LPUART5,
  54. PER_CLK_LPUART6,
  55. PER_CLK_LPUART7,
  56. };
  57. for (index = 0; index < 8; index++) {
  58. if (lpuart_array[index] == LPUART_BASE)
  59. break;
  60. }
  61. if (index < 4 || index > 7)
  62. return 0;
  63. return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
  64. }
  65. #ifdef CONFIG_SYS_I2C_IMX_LPI2C
  66. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  67. {
  68. /* Set parent to FIRC DIV2 clock */
  69. const enum pcc_clk lpi2c_pcc_clks[] = {
  70. PER_CLK_LPI2C4,
  71. PER_CLK_LPI2C5,
  72. PER_CLK_LPI2C6,
  73. PER_CLK_LPI2C7,
  74. };
  75. if (i2c_num < 4 || i2c_num > 7)
  76. return -EINVAL;
  77. if (enable) {
  78. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  79. pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
  80. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
  81. } else {
  82. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  83. }
  84. return 0;
  85. }
  86. u32 imx_get_i2cclk(unsigned i2c_num)
  87. {
  88. const enum pcc_clk lpi2c_pcc_clks[] = {
  89. PER_CLK_LPI2C4,
  90. PER_CLK_LPI2C5,
  91. PER_CLK_LPI2C6,
  92. PER_CLK_LPI2C7,
  93. };
  94. if (i2c_num < 4 || i2c_num > 7)
  95. return 0;
  96. return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
  97. }
  98. #endif
  99. unsigned int mxc_get_clock(enum mxc_clock clk)
  100. {
  101. switch (clk) {
  102. case MXC_ARM_CLK:
  103. return scg_clk_get_rate(SCG_CORE_CLK);
  104. case MXC_AXI_CLK:
  105. return get_fast_plat_clk();
  106. case MXC_AHB_CLK:
  107. return get_slow_plat_clk();
  108. case MXC_IPG_CLK:
  109. return get_ipg_clk();
  110. case MXC_I2C_CLK:
  111. return pcc_clock_get_rate(PER_CLK_LPI2C4);
  112. case MXC_UART_CLK:
  113. return get_lpuart_clk();
  114. case MXC_ESDHC_CLK:
  115. return pcc_clock_get_rate(PER_CLK_USDHC0);
  116. case MXC_ESDHC2_CLK:
  117. return pcc_clock_get_rate(PER_CLK_USDHC1);
  118. case MXC_DDR_CLK:
  119. return scg_clk_get_rate(SCG_DDR_CLK);
  120. default:
  121. printf("Unsupported mxc_clock %d\n", clk);
  122. break;
  123. }
  124. return 0;
  125. }
  126. void init_clk_usdhc(u32 index)
  127. {
  128. switch (index) {
  129. case 0:
  130. /*Disable the clock before configure it */
  131. pcc_clock_enable(PER_CLK_USDHC0, false);
  132. /* 158MHz / 1 = 158MHz */
  133. pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
  134. pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
  135. pcc_clock_enable(PER_CLK_USDHC0, true);
  136. break;
  137. case 1:
  138. /*Disable the clock before configure it */
  139. pcc_clock_enable(PER_CLK_USDHC1, false);
  140. /* 158MHz / 1 = 158MHz */
  141. pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
  142. pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
  143. pcc_clock_enable(PER_CLK_USDHC1, true);
  144. break;
  145. default:
  146. printf("Invalid index for USDHC %d\n", index);
  147. break;
  148. }
  149. }
  150. #ifdef CONFIG_MXC_OCOTP
  151. #define OCOTP_CTRL_PCC1_SLOT (38)
  152. #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
  153. void enable_ocotp_clk(unsigned char enable)
  154. {
  155. u32 val;
  156. /*
  157. * Seems the OCOTP CLOCKs have been enabled at default,
  158. * check its inuse flag
  159. */
  160. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
  161. if (!(val & PCC_INUSE_MASK))
  162. writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
  163. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
  164. if (!(val & PCC_INUSE_MASK))
  165. writel(PCC_CGC_MASK,
  166. (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
  167. }
  168. #endif
  169. void enable_usboh3_clk(unsigned char enable)
  170. {
  171. if (enable) {
  172. pcc_clock_enable(PER_CLK_USB0, false);
  173. pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
  174. pcc_clock_enable(PER_CLK_USB0, true);
  175. #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
  176. if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
  177. pcc_clock_enable(PER_CLK_USB1, false);
  178. pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
  179. pcc_clock_enable(PER_CLK_USB1, true);
  180. }
  181. #endif
  182. pcc_clock_enable(PER_CLK_USB_PHY, true);
  183. pcc_clock_enable(PER_CLK_USB_PL301, true);
  184. } else {
  185. pcc_clock_enable(PER_CLK_USB0, false);
  186. pcc_clock_enable(PER_CLK_USB1, false);
  187. pcc_clock_enable(PER_CLK_USB_PHY, false);
  188. pcc_clock_enable(PER_CLK_USB_PL301, false);
  189. }
  190. }
  191. static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
  192. {
  193. const enum pcc_clk lpuart_pcc_clks[] = {
  194. PER_CLK_LPUART4,
  195. PER_CLK_LPUART5,
  196. PER_CLK_LPUART6,
  197. PER_CLK_LPUART7,
  198. };
  199. if (index < 4 || index > 7)
  200. return;
  201. #ifndef CONFIG_CLK_DEBUG
  202. pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
  203. #endif
  204. pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
  205. pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
  206. }
  207. static void init_clk_lpuart(void)
  208. {
  209. u32 index = 0, i;
  210. const u32 lpuart_array[] = {
  211. LPUART0_RBASE,
  212. LPUART1_RBASE,
  213. LPUART2_RBASE,
  214. LPUART3_RBASE,
  215. LPUART4_RBASE,
  216. LPUART5_RBASE,
  217. LPUART6_RBASE,
  218. LPUART7_RBASE,
  219. };
  220. for (i = 0; i < 8; i++) {
  221. if (lpuart_array[i] == LPUART_BASE) {
  222. index = i;
  223. break;
  224. }
  225. }
  226. lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
  227. }
  228. static void init_clk_rgpio2p(void)
  229. {
  230. /*Enable RGPIO2P1 clock */
  231. pcc_clock_enable(PER_CLK_RGPIO2P1, true);
  232. /*
  233. * Hard code to enable RGPIO2P0 clock since it is not
  234. * in clock frame for A7 domain
  235. */
  236. writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
  237. }
  238. /* Configure PLL/PFD freq */
  239. void clock_init(void)
  240. {
  241. /*
  242. * ROM has enabled clocks:
  243. * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
  244. * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
  245. * A7 side: SPLL PFD0 (scs selected, 413Mhz),
  246. * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
  247. * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
  248. * IP BUS (NIC1_BUS) = 58.6Mhz
  249. *
  250. * In u-boot:
  251. * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
  252. * 2. Enable USB PLL
  253. * 3. Init the clocks of peripherals used in u-boot bu
  254. * without set rate interface.The clocks for these
  255. * peripherals are enabled in this intialization.
  256. * 4.Other peripherals with set clock rate interface
  257. * does not be set in this function.
  258. */
  259. scg_a7_firc_init();
  260. scg_a7_soscdiv_init();
  261. scg_a7_init_core_clk();
  262. /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
  263. scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
  264. scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
  265. scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
  266. init_clk_lpuart();
  267. init_clk_rgpio2p();
  268. enable_usboh3_clk(1);
  269. }
  270. #ifdef CONFIG_IMX_HAB
  271. void hab_caam_clock_enable(unsigned char enable)
  272. {
  273. if (enable)
  274. pcc_clock_enable(PER_CLK_CAAM, true);
  275. else
  276. pcc_clock_enable(PER_CLK_CAAM, false);
  277. }
  278. #endif
  279. #ifndef CONFIG_SPL_BUILD
  280. /*
  281. * Dump some core clockes.
  282. */
  283. int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  284. char *const argv[])
  285. {
  286. u32 freq;
  287. freq = decode_pll(PLL_A7_SPLL);
  288. printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
  289. freq = decode_pll(PLL_A7_APLL);
  290. printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
  291. freq = decode_pll(PLL_USB);
  292. printf("PLL_USB %8d MHz\n", freq / 1000000);
  293. printf("\n");
  294. printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
  295. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  296. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  297. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  298. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  299. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  300. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  301. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  302. printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
  303. scg_a7_info();
  304. return 0;
  305. }
  306. U_BOOT_CMD(
  307. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  308. "display clocks",
  309. ""
  310. );
  311. #endif