clock.c 28 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <div64.h>
  12. #include <log.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <linux/errno.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/sys_proto.h>
  20. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  21. ANATOP_BASE_ADDR;
  22. struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23. #ifdef CONFIG_FSL_ESDHC_IMX
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #endif
  26. int get_clocks(void)
  27. {
  28. #ifdef CONFIG_FSL_ESDHC_IMX
  29. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
  30. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  31. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
  32. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  33. #else
  34. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  35. #endif
  36. #endif
  37. return 0;
  38. }
  39. u32 get_ahb_clk(void)
  40. {
  41. return get_root_clk(AHB_CLK_ROOT);
  42. }
  43. static u32 get_ipg_clk(void)
  44. {
  45. /*
  46. * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
  47. * each other.
  48. */
  49. return get_ahb_clk() / 2;
  50. }
  51. u32 imx_get_uartclk(void)
  52. {
  53. return get_root_clk(UART_CLK_ROOT);
  54. }
  55. u32 imx_get_fecclk(void)
  56. {
  57. return get_root_clk(ENET_AXI_CLK_ROOT);
  58. }
  59. #ifdef CONFIG_MXC_OCOTP
  60. void enable_ocotp_clk(unsigned char enable)
  61. {
  62. clock_enable(CCGR_OCOTP, enable);
  63. }
  64. void enable_thermal_clk(void)
  65. {
  66. enable_ocotp_clk(1);
  67. }
  68. #endif
  69. void enable_usboh3_clk(unsigned char enable)
  70. {
  71. u32 target;
  72. if (enable) {
  73. /* disable the clock gate first */
  74. clock_enable(CCGR_USB_HSIC, 0);
  75. /* 120Mhz */
  76. target = CLK_ROOT_ON |
  77. USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  78. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  79. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  80. clock_set_target_val(USB_HSIC_CLK_ROOT, target);
  81. /* enable the clock gate */
  82. clock_enable(CCGR_USB_CTRL, 1);
  83. clock_enable(CCGR_USB_HSIC, 1);
  84. clock_enable(CCGR_USB_PHY1, 1);
  85. clock_enable(CCGR_USB_PHY2, 1);
  86. } else {
  87. clock_enable(CCGR_USB_CTRL, 0);
  88. clock_enable(CCGR_USB_HSIC, 0);
  89. clock_enable(CCGR_USB_PHY1, 0);
  90. clock_enable(CCGR_USB_PHY2, 0);
  91. }
  92. }
  93. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  94. {
  95. u32 reg, div_sel;
  96. u32 num, denom;
  97. /*
  98. * Alought there are four choices for the bypass src,
  99. * we choose OSC_24M which is the default set in ROM.
  100. */
  101. switch (pll) {
  102. case PLL_CORE:
  103. reg = readl(&ccm_anatop->pll_arm);
  104. if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
  105. return 0;
  106. if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
  107. return MXC_HCLK;
  108. div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
  109. CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
  110. return (infreq * div_sel) / 2;
  111. case PLL_SYS:
  112. reg = readl(&ccm_anatop->pll_480);
  113. if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
  114. return 0;
  115. if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
  116. return MXC_HCLK;
  117. if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
  118. CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
  119. return 480000000u;
  120. else
  121. return 528000000u;
  122. case PLL_ENET:
  123. reg = readl(&ccm_anatop->pll_enet);
  124. if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
  125. return 0;
  126. if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
  127. return MXC_HCLK;
  128. return 1000000000u;
  129. case PLL_DDR:
  130. reg = readl(&ccm_anatop->pll_ddr);
  131. if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
  132. return 0;
  133. num = ccm_anatop->pll_ddr_num;
  134. denom = ccm_anatop->pll_ddr_denom;
  135. if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
  136. return MXC_HCLK;
  137. div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
  138. CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
  139. return infreq * (div_sel + num / denom);
  140. case PLL_USB:
  141. return 480000000u;
  142. default:
  143. printf("Unsupported pll clocks %d\n", pll);
  144. break;
  145. }
  146. return 0;
  147. }
  148. static u32 mxc_get_pll_sys_derive(int derive)
  149. {
  150. u32 freq, div, frac;
  151. u32 reg;
  152. div = 1;
  153. reg = readl(&ccm_anatop->pll_480);
  154. freq = decode_pll(PLL_SYS, MXC_HCLK);
  155. switch (derive) {
  156. case PLL_SYS_MAIN_480M_CLK:
  157. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
  158. return 0;
  159. else
  160. return freq;
  161. case PLL_SYS_MAIN_240M_CLK:
  162. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
  163. return 0;
  164. else
  165. return freq / 2;
  166. case PLL_SYS_MAIN_120M_CLK:
  167. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
  168. return 0;
  169. else
  170. return freq / 4;
  171. case PLL_SYS_PFD0_392M_CLK:
  172. reg = readl(&ccm_anatop->pfd_480a);
  173. if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
  174. return 0;
  175. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  176. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  177. break;
  178. case PLL_SYS_PFD0_196M_CLK:
  179. if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
  180. return 0;
  181. reg = readl(&ccm_anatop->pfd_480a);
  182. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  183. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  184. div = 2;
  185. break;
  186. case PLL_SYS_PFD1_332M_CLK:
  187. reg = readl(&ccm_anatop->pfd_480a);
  188. if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
  189. return 0;
  190. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  191. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  192. break;
  193. case PLL_SYS_PFD1_166M_CLK:
  194. if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
  195. return 0;
  196. reg = readl(&ccm_anatop->pfd_480a);
  197. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  198. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  199. div = 2;
  200. break;
  201. case PLL_SYS_PFD2_270M_CLK:
  202. reg = readl(&ccm_anatop->pfd_480a);
  203. if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
  204. return 0;
  205. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  206. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  207. break;
  208. case PLL_SYS_PFD2_135M_CLK:
  209. if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
  210. return 0;
  211. reg = readl(&ccm_anatop->pfd_480a);
  212. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  213. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  214. div = 2;
  215. break;
  216. case PLL_SYS_PFD3_CLK:
  217. reg = readl(&ccm_anatop->pfd_480a);
  218. if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
  219. return 0;
  220. frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
  221. CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
  222. break;
  223. case PLL_SYS_PFD4_CLK:
  224. reg = readl(&ccm_anatop->pfd_480b);
  225. if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
  226. return 0;
  227. frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
  228. CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
  229. break;
  230. case PLL_SYS_PFD5_CLK:
  231. reg = readl(&ccm_anatop->pfd_480b);
  232. if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
  233. return 0;
  234. frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
  235. CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
  236. break;
  237. case PLL_SYS_PFD6_CLK:
  238. reg = readl(&ccm_anatop->pfd_480b);
  239. if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
  240. return 0;
  241. frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
  242. CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
  243. break;
  244. case PLL_SYS_PFD7_CLK:
  245. reg = readl(&ccm_anatop->pfd_480b);
  246. if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
  247. return 0;
  248. frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
  249. CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
  250. break;
  251. default:
  252. printf("Error derived pll_sys clock %d\n", derive);
  253. return 0;
  254. }
  255. return ((freq / frac) * 18) / div;
  256. }
  257. static u32 mxc_get_pll_enet_derive(int derive)
  258. {
  259. u32 freq, reg;
  260. freq = decode_pll(PLL_ENET, MXC_HCLK);
  261. reg = readl(&ccm_anatop->pll_enet);
  262. switch (derive) {
  263. case PLL_ENET_MAIN_500M_CLK:
  264. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
  265. return freq / 2;
  266. break;
  267. case PLL_ENET_MAIN_250M_CLK:
  268. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
  269. return freq / 4;
  270. break;
  271. case PLL_ENET_MAIN_125M_CLK:
  272. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
  273. return freq / 8;
  274. break;
  275. case PLL_ENET_MAIN_100M_CLK:
  276. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
  277. return freq / 10;
  278. break;
  279. case PLL_ENET_MAIN_50M_CLK:
  280. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
  281. return freq / 20;
  282. break;
  283. case PLL_ENET_MAIN_40M_CLK:
  284. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
  285. return freq / 25;
  286. break;
  287. case PLL_ENET_MAIN_25M_CLK:
  288. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
  289. return freq / 40;
  290. break;
  291. default:
  292. printf("Error derived pll_enet clock %d\n", derive);
  293. break;
  294. }
  295. return 0;
  296. }
  297. static u32 mxc_get_pll_ddr_derive(int derive)
  298. {
  299. u32 freq, reg;
  300. freq = decode_pll(PLL_DDR, MXC_HCLK);
  301. reg = readl(&ccm_anatop->pll_ddr);
  302. switch (derive) {
  303. case PLL_DRAM_MAIN_1066M_CLK:
  304. return freq;
  305. case PLL_DRAM_MAIN_533M_CLK:
  306. if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
  307. return freq / 2;
  308. break;
  309. default:
  310. printf("Error derived pll_ddr clock %d\n", derive);
  311. break;
  312. }
  313. return 0;
  314. }
  315. static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
  316. {
  317. switch (pll) {
  318. case PLL_SYS:
  319. return mxc_get_pll_sys_derive(derive);
  320. case PLL_ENET:
  321. return mxc_get_pll_enet_derive(derive);
  322. case PLL_DDR:
  323. return mxc_get_pll_ddr_derive(derive);
  324. default:
  325. printf("Error pll.\n");
  326. return 0;
  327. }
  328. }
  329. static u32 get_root_src_clk(enum clk_root_src root_src)
  330. {
  331. switch (root_src) {
  332. case OSC_24M_CLK:
  333. return 24000000u;
  334. case PLL_ARM_MAIN_800M_CLK:
  335. return decode_pll(PLL_CORE, MXC_HCLK);
  336. case PLL_SYS_MAIN_480M_CLK:
  337. case PLL_SYS_MAIN_240M_CLK:
  338. case PLL_SYS_MAIN_120M_CLK:
  339. case PLL_SYS_PFD0_392M_CLK:
  340. case PLL_SYS_PFD0_196M_CLK:
  341. case PLL_SYS_PFD1_332M_CLK:
  342. case PLL_SYS_PFD1_166M_CLK:
  343. case PLL_SYS_PFD2_270M_CLK:
  344. case PLL_SYS_PFD2_135M_CLK:
  345. case PLL_SYS_PFD3_CLK:
  346. case PLL_SYS_PFD4_CLK:
  347. case PLL_SYS_PFD5_CLK:
  348. case PLL_SYS_PFD6_CLK:
  349. case PLL_SYS_PFD7_CLK:
  350. return mxc_get_pll_derive(PLL_SYS, root_src);
  351. case PLL_ENET_MAIN_500M_CLK:
  352. case PLL_ENET_MAIN_250M_CLK:
  353. case PLL_ENET_MAIN_125M_CLK:
  354. case PLL_ENET_MAIN_100M_CLK:
  355. case PLL_ENET_MAIN_50M_CLK:
  356. case PLL_ENET_MAIN_40M_CLK:
  357. case PLL_ENET_MAIN_25M_CLK:
  358. return mxc_get_pll_derive(PLL_ENET, root_src);
  359. case PLL_DRAM_MAIN_1066M_CLK:
  360. case PLL_DRAM_MAIN_533M_CLK:
  361. return mxc_get_pll_derive(PLL_DDR, root_src);
  362. case PLL_AUDIO_MAIN_CLK:
  363. return decode_pll(PLL_AUDIO, MXC_HCLK);
  364. case PLL_VIDEO_MAIN_CLK:
  365. return decode_pll(PLL_VIDEO, MXC_HCLK);
  366. case PLL_USB_MAIN_480M_CLK:
  367. return decode_pll(PLL_USB, MXC_HCLK);
  368. case REF_1M_CLK:
  369. return 1000000;
  370. case OSC_32K_CLK:
  371. return MXC_CLK32;
  372. case EXT_CLK_1:
  373. case EXT_CLK_2:
  374. case EXT_CLK_3:
  375. case EXT_CLK_4:
  376. printf("No EXT CLK supported??\n");
  377. break;
  378. };
  379. return 0;
  380. }
  381. u32 get_root_clk(enum clk_root_index clock_id)
  382. {
  383. enum clk_root_src root_src;
  384. u32 post_podf, pre_podf, auto_podf, root_src_clk;
  385. int auto_en;
  386. if (clock_root_enabled(clock_id) <= 0)
  387. return 0;
  388. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  389. return 0;
  390. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  391. return 0;
  392. if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
  393. return 0;
  394. if (auto_en == 0)
  395. auto_podf = 0;
  396. if (clock_get_src(clock_id, &root_src) < 0)
  397. return 0;
  398. root_src_clk = get_root_src_clk(root_src);
  399. /*
  400. * bypass clk is ignored.
  401. */
  402. return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
  403. (auto_podf + 1);
  404. }
  405. static u32 get_ddrc_clk(void)
  406. {
  407. u32 reg, freq;
  408. enum root_post_div post_div;
  409. reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
  410. if (reg & CLK_ROOT_MUX_MASK)
  411. /* DRAM_ALT_CLK_ROOT */
  412. freq = get_root_clk(DRAM_ALT_CLK_ROOT);
  413. else
  414. /* PLL_DRAM_MAIN_1066M_CLK */
  415. freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
  416. post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
  417. return freq / (post_div + 1) / 2;
  418. }
  419. unsigned int mxc_get_clock(enum mxc_clock clk)
  420. {
  421. switch (clk) {
  422. case MXC_ARM_CLK:
  423. return get_root_clk(ARM_A7_CLK_ROOT);
  424. case MXC_AXI_CLK:
  425. return get_root_clk(MAIN_AXI_CLK_ROOT);
  426. case MXC_AHB_CLK:
  427. return get_root_clk(AHB_CLK_ROOT);
  428. case MXC_IPG_CLK:
  429. return get_ipg_clk();
  430. case MXC_I2C_CLK:
  431. return get_root_clk(I2C1_CLK_ROOT);
  432. case MXC_UART_CLK:
  433. return get_root_clk(UART1_CLK_ROOT);
  434. case MXC_CSPI_CLK:
  435. return get_root_clk(ECSPI1_CLK_ROOT);
  436. case MXC_DDR_CLK:
  437. return get_ddrc_clk();
  438. case MXC_ESDHC_CLK:
  439. return get_root_clk(USDHC1_CLK_ROOT);
  440. case MXC_ESDHC2_CLK:
  441. return get_root_clk(USDHC2_CLK_ROOT);
  442. case MXC_ESDHC3_CLK:
  443. return get_root_clk(USDHC3_CLK_ROOT);
  444. default:
  445. printf("Unsupported mxc_clock %d\n", clk);
  446. break;
  447. }
  448. return 0;
  449. }
  450. #ifdef CONFIG_SYS_I2C_MXC
  451. /* i2c_num can be 0 - 3 */
  452. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  453. {
  454. u32 target;
  455. if (i2c_num >= 4)
  456. return -EINVAL;
  457. if (enable) {
  458. clock_enable(CCGR_I2C1 + i2c_num, 0);
  459. /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
  460. target = CLK_ROOT_ON |
  461. I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  462. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  463. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  464. clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
  465. clock_enable(CCGR_I2C1 + i2c_num, 1);
  466. } else {
  467. clock_enable(CCGR_I2C1 + i2c_num, 0);
  468. }
  469. return 0;
  470. }
  471. #endif
  472. static void init_clk_esdhc(void)
  473. {
  474. u32 target;
  475. /* disable the clock gate first */
  476. clock_enable(CCGR_USDHC1, 0);
  477. clock_enable(CCGR_USDHC2, 0);
  478. clock_enable(CCGR_USDHC3, 0);
  479. /* 196: 392/2 */
  480. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  481. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  482. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  483. clock_set_target_val(USDHC1_CLK_ROOT, target);
  484. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  485. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  486. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  487. clock_set_target_val(USDHC2_CLK_ROOT, target);
  488. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  489. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  490. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  491. clock_set_target_val(USDHC3_CLK_ROOT, target);
  492. /* enable the clock gate */
  493. clock_enable(CCGR_USDHC1, 1);
  494. clock_enable(CCGR_USDHC2, 1);
  495. clock_enable(CCGR_USDHC3, 1);
  496. }
  497. static void init_clk_uart(void)
  498. {
  499. u32 target;
  500. /* disable the clock gate first */
  501. clock_enable(CCGR_UART1, 0);
  502. clock_enable(CCGR_UART2, 0);
  503. clock_enable(CCGR_UART3, 0);
  504. clock_enable(CCGR_UART4, 0);
  505. clock_enable(CCGR_UART5, 0);
  506. clock_enable(CCGR_UART6, 0);
  507. clock_enable(CCGR_UART7, 0);
  508. /* 24Mhz */
  509. target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
  510. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  511. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  512. clock_set_target_val(UART1_CLK_ROOT, target);
  513. target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
  514. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  515. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  516. clock_set_target_val(UART2_CLK_ROOT, target);
  517. target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
  518. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  519. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  520. clock_set_target_val(UART3_CLK_ROOT, target);
  521. target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
  522. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  523. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  524. clock_set_target_val(UART4_CLK_ROOT, target);
  525. target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
  526. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  527. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  528. clock_set_target_val(UART5_CLK_ROOT, target);
  529. target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
  530. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  531. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  532. clock_set_target_val(UART6_CLK_ROOT, target);
  533. target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
  534. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  535. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  536. clock_set_target_val(UART7_CLK_ROOT, target);
  537. /* enable the clock gate */
  538. clock_enable(CCGR_UART1, 1);
  539. clock_enable(CCGR_UART2, 1);
  540. clock_enable(CCGR_UART3, 1);
  541. clock_enable(CCGR_UART4, 1);
  542. clock_enable(CCGR_UART5, 1);
  543. clock_enable(CCGR_UART6, 1);
  544. clock_enable(CCGR_UART7, 1);
  545. }
  546. static void init_clk_weim(void)
  547. {
  548. u32 target;
  549. /* disable the clock gate first */
  550. clock_enable(CCGR_WEIM, 0);
  551. /* 120Mhz */
  552. target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  553. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  554. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  555. clock_set_target_val(EIM_CLK_ROOT, target);
  556. /* enable the clock gate */
  557. clock_enable(CCGR_WEIM, 1);
  558. }
  559. static void init_clk_ecspi(void)
  560. {
  561. u32 target;
  562. /* disable the clock gate first */
  563. clock_enable(CCGR_ECSPI1, 0);
  564. clock_enable(CCGR_ECSPI2, 0);
  565. clock_enable(CCGR_ECSPI3, 0);
  566. clock_enable(CCGR_ECSPI4, 0);
  567. /* 60Mhz: 240/4 */
  568. target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  569. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  570. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  571. clock_set_target_val(ECSPI1_CLK_ROOT, target);
  572. target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  573. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  574. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  575. clock_set_target_val(ECSPI2_CLK_ROOT, target);
  576. target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  577. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  578. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  579. clock_set_target_val(ECSPI3_CLK_ROOT, target);
  580. target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  581. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  582. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  583. clock_set_target_val(ECSPI4_CLK_ROOT, target);
  584. /* enable the clock gate */
  585. clock_enable(CCGR_ECSPI1, 1);
  586. clock_enable(CCGR_ECSPI2, 1);
  587. clock_enable(CCGR_ECSPI3, 1);
  588. clock_enable(CCGR_ECSPI4, 1);
  589. }
  590. static void init_clk_wdog(void)
  591. {
  592. u32 target;
  593. /* disable the clock gate first */
  594. clock_enable(CCGR_WDOG1, 0);
  595. clock_enable(CCGR_WDOG2, 0);
  596. clock_enable(CCGR_WDOG3, 0);
  597. clock_enable(CCGR_WDOG4, 0);
  598. /* 24Mhz */
  599. target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
  600. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  601. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  602. clock_set_target_val(WDOG_CLK_ROOT, target);
  603. /* enable the clock gate */
  604. clock_enable(CCGR_WDOG1, 1);
  605. clock_enable(CCGR_WDOG2, 1);
  606. clock_enable(CCGR_WDOG3, 1);
  607. clock_enable(CCGR_WDOG4, 1);
  608. }
  609. #ifdef CONFIG_MXC_EPDC
  610. static void init_clk_epdc(void)
  611. {
  612. u32 target;
  613. /* disable the clock gate first */
  614. clock_enable(CCGR_EPDC, 0);
  615. /* 24Mhz */
  616. target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  617. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  618. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
  619. clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
  620. /* enable the clock gate */
  621. clock_enable(CCGR_EPDC, 1);
  622. }
  623. #endif
  624. static int enable_pll_enet(void)
  625. {
  626. u32 reg;
  627. s32 timeout = 100000;
  628. reg = readl(&ccm_anatop->pll_enet);
  629. /* If pll_enet powered up, no need to set it again */
  630. if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
  631. reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
  632. writel(reg, &ccm_anatop->pll_enet);
  633. while (timeout--) {
  634. if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
  635. break;
  636. }
  637. if (timeout <= 0) {
  638. /* If timeout, we set pwdn for pll_enet. */
  639. reg |= ANADIG_PLL_ENET_PWDN_MASK;
  640. return -ETIME;
  641. }
  642. }
  643. /* Clear bypass */
  644. writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
  645. writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
  646. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
  647. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
  648. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
  649. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
  650. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
  651. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
  652. &ccm_anatop->pll_enet_set);
  653. return 0;
  654. }
  655. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  656. u32 post_div)
  657. {
  658. u32 reg = 0;
  659. ulong start;
  660. debug("pll5 div = %d, num = %d, denom = %d\n",
  661. pll_div, pll_num, pll_denom);
  662. /* Power up PLL5 video and disable its output */
  663. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
  664. CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
  665. CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
  666. CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
  667. CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
  668. CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
  669. &ccm_anatop->pll_video_clr);
  670. /* Set div, num and denom */
  671. switch (post_div) {
  672. case 1:
  673. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  674. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
  675. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  676. &ccm_anatop->pll_video_set);
  677. break;
  678. case 2:
  679. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  680. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  681. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  682. &ccm_anatop->pll_video_set);
  683. break;
  684. case 3:
  685. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  686. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  687. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
  688. &ccm_anatop->pll_video_set);
  689. break;
  690. case 4:
  691. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  692. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  693. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
  694. &ccm_anatop->pll_video_set);
  695. break;
  696. case 0:
  697. default:
  698. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  699. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
  700. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  701. &ccm_anatop->pll_video_set);
  702. break;
  703. }
  704. writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
  705. &ccm_anatop->pll_video_num);
  706. writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
  707. &ccm_anatop->pll_video_denom);
  708. /* Wait PLL5 lock */
  709. start = get_timer(0); /* Get current timestamp */
  710. do {
  711. reg = readl(&ccm_anatop->pll_video);
  712. if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
  713. /* Enable PLL out */
  714. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
  715. &ccm_anatop->pll_video_set);
  716. return 0;
  717. }
  718. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  719. printf("Lock PLL5 timeout\n");
  720. return 1;
  721. }
  722. int set_clk_qspi(void)
  723. {
  724. u32 target;
  725. /* disable the clock gate first */
  726. clock_enable(CCGR_QSPI, 0);
  727. /* 49M: 392/2/4 */
  728. target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  729. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  730. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  731. clock_set_target_val(QSPI_CLK_ROOT, target);
  732. /* enable the clock gate */
  733. clock_enable(CCGR_QSPI, 1);
  734. return 0;
  735. }
  736. int set_clk_nand(void)
  737. {
  738. u32 target;
  739. /* disable the clock gate first */
  740. clock_enable(CCGR_RAWNAND, 0);
  741. enable_pll_enet();
  742. /* 100: 500/5 */
  743. target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
  744. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  745. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
  746. clock_set_target_val(NAND_CLK_ROOT, target);
  747. /* enable the clock gate */
  748. clock_enable(CCGR_RAWNAND, 1);
  749. return 0;
  750. }
  751. void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
  752. {
  753. u32 hck = MXC_HCLK/1000;
  754. u32 min = hck * 27;
  755. u32 max = hck * 54;
  756. u32 temp, best = 0;
  757. u32 i, j, pred = 1, postd = 1;
  758. u32 pll_div, pll_num, pll_denom, post_div = 0;
  759. u32 target;
  760. debug("mxs_set_lcdclk, freq = %d\n", freq);
  761. clock_enable(CCGR_LCDIF, 0);
  762. temp = (freq * 8 * 8);
  763. if (temp < min) {
  764. for (i = 1; i <= 4; i++) {
  765. if ((temp * (1 << i)) > min) {
  766. post_div = i;
  767. freq = (freq * (1 << i));
  768. break;
  769. }
  770. }
  771. if (5 == i) {
  772. printf("Fail to set rate to %u kHz", freq);
  773. return;
  774. }
  775. }
  776. for (i = 1; i <= 8; i++) {
  777. for (j = 1; j <= 8; j++) {
  778. temp = freq * i * j;
  779. if (temp > max || temp < min)
  780. continue;
  781. if (best == 0 || temp < best) {
  782. best = temp;
  783. pred = i;
  784. postd = j;
  785. }
  786. }
  787. }
  788. if (best == 0) {
  789. printf("Fail to set rate to %u kHz", freq);
  790. return;
  791. }
  792. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  793. pll_div = best / hck;
  794. pll_denom = 1000000;
  795. pll_num = (best - hck * pll_div) * pll_denom / hck;
  796. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  797. return;
  798. target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
  799. CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
  800. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
  801. clock_enable(CCGR_LCDIF, 1);
  802. }
  803. #ifdef CONFIG_FEC_MXC
  804. int set_clk_enet(enum enet_freq type)
  805. {
  806. u32 target;
  807. int ret;
  808. u32 enet1_ref, enet2_ref;
  809. /* disable the clock first */
  810. clock_enable(CCGR_ENET1, 0);
  811. clock_enable(CCGR_ENET2, 0);
  812. switch (type) {
  813. case ENET_125MHZ:
  814. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  815. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  816. break;
  817. case ENET_50MHZ:
  818. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  819. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  820. break;
  821. case ENET_25MHZ:
  822. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  823. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  824. break;
  825. default:
  826. return -EINVAL;
  827. }
  828. ret = enable_pll_enet();
  829. if (ret != 0)
  830. return ret;
  831. /* set enet axi clock 196M: 392/2 */
  832. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  833. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  834. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  835. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  836. target = CLK_ROOT_ON | enet1_ref |
  837. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  838. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  839. clock_set_target_val(ENET1_REF_CLK_ROOT, target);
  840. target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  841. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  842. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  843. clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
  844. target = CLK_ROOT_ON | enet2_ref |
  845. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  846. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  847. clock_set_target_val(ENET2_REF_CLK_ROOT, target);
  848. target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  849. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  850. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  851. clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
  852. #ifdef CONFIG_FEC_MXC_25M_REF_CLK
  853. target = CLK_ROOT_ON |
  854. ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  855. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  856. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  857. clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
  858. #endif
  859. /* enable clock */
  860. clock_enable(CCGR_ENET1, 1);
  861. clock_enable(CCGR_ENET2, 1);
  862. return 0;
  863. }
  864. #endif
  865. /* Configure PLL/PFD freq */
  866. void clock_init(void)
  867. {
  868. /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  869. * In u-boot, we have to:
  870. * 1. Configure PFD3- PFD7 for freq we needed in u-boot
  871. * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
  872. * interface. The clocks for these peripherals are enabled after this intialization.
  873. * 3. Other peripherals with set clock rate interface does not be set in this function.
  874. */
  875. u32 reg;
  876. /*
  877. * Configure PFD4 to 392M
  878. * 480M * 18 / 0x16 = 392M
  879. */
  880. reg = readl(&ccm_anatop->pfd_480b);
  881. reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
  882. CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
  883. reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
  884. writel(reg, &ccm_anatop->pfd_480b);
  885. init_clk_esdhc();
  886. init_clk_uart();
  887. init_clk_weim();
  888. init_clk_ecspi();
  889. init_clk_wdog();
  890. #ifdef CONFIG_MXC_EPDC
  891. init_clk_epdc();
  892. #endif
  893. enable_usboh3_clk(1);
  894. clock_enable(CCGR_SNVS, 1);
  895. #ifdef CONFIG_NAND_MXS
  896. clock_enable(CCGR_RAWNAND, 1);
  897. #endif
  898. if (IS_ENABLED(CONFIG_IMX_RDC)) {
  899. clock_enable(CCGR_RDC, 1);
  900. clock_enable(CCGR_SEMA1, 1);
  901. clock_enable(CCGR_SEMA2, 1);
  902. }
  903. }
  904. #ifdef CONFIG_IMX_HAB
  905. void hab_caam_clock_enable(unsigned char enable)
  906. {
  907. if (enable)
  908. clock_enable(CCGR_CAAM, 1);
  909. else
  910. clock_enable(CCGR_CAAM, 0);
  911. }
  912. #endif
  913. #ifdef CONFIG_MXC_EPDC
  914. void epdc_clock_enable(void)
  915. {
  916. clock_enable(CCGR_EPDC, 1);
  917. }
  918. void epdc_clock_disable(void)
  919. {
  920. clock_enable(CCGR_EPDC, 0);
  921. }
  922. #endif
  923. #ifndef CONFIG_SPL_BUILD
  924. /*
  925. * Dump some core clockes.
  926. */
  927. int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  928. char *const argv[])
  929. {
  930. u32 freq;
  931. freq = decode_pll(PLL_CORE, MXC_HCLK);
  932. printf("PLL_CORE %8d MHz\n", freq / 1000000);
  933. freq = decode_pll(PLL_SYS, MXC_HCLK);
  934. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  935. freq = decode_pll(PLL_ENET, MXC_HCLK);
  936. printf("PLL_NET %8d MHz\n", freq / 1000000);
  937. printf("\n");
  938. printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  939. printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  940. #ifdef CONFIG_MXC_SPI
  941. printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  942. #endif
  943. printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  944. printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  945. printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  946. printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  947. printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  948. printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  949. return 0;
  950. }
  951. U_BOOT_CMD(
  952. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  953. "display clocks",
  954. ""
  955. );
  956. #endif