opos6ul.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Armadeus Systems
  4. */
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/crm_regs.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <common.h>
  13. #include <env.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #ifdef CONFIG_FEC_MXC
  16. #include <miiphy.h>
  17. int board_phy_config(struct phy_device *phydev)
  18. {
  19. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  20. if (phydev->drv->config)
  21. phydev->drv->config(phydev);
  22. return 0;
  23. }
  24. static int setup_fec(void)
  25. {
  26. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  27. /* Use 50M anatop loopback REF_CLK1 for ENET1,
  28. * clear gpr1[13], set gpr1[17] */
  29. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  30. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  31. return enable_fec_anatop_clock(0, ENET_50MHZ);
  32. }
  33. #endif /* CONFIG_FEC_MXC */
  34. int board_init(void)
  35. {
  36. /* Address of boot parameters */
  37. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  38. #ifdef CONFIG_FEC_MXC
  39. setup_fec();
  40. #endif
  41. return 0;
  42. }
  43. int __weak opos6ul_board_late_init(void)
  44. {
  45. return 0;
  46. }
  47. int board_late_init(void)
  48. {
  49. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  50. unsigned reg = readl(&psrc->sbmr2);
  51. /* In bootstrap don't use the env vars */
  52. if (((reg & 0x3000000) >> 24) == 0x1) {
  53. env_set_default(NULL, 0);
  54. env_set("preboot", "");
  55. }
  56. return opos6ul_board_late_init();
  57. }
  58. int dram_init(void)
  59. {
  60. gd->ram_size = imx_ddr_size();
  61. return 0;
  62. }
  63. #ifdef CONFIG_SPL_BUILD
  64. #include <asm/arch/mx6-ddr.h>
  65. #include <linux/libfdt.h>
  66. #include <spl.h>
  67. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  68. .grp_addds = 0x00000030,
  69. .grp_ddrmode_ctl = 0x00020000,
  70. .grp_b0ds = 0x00000030,
  71. .grp_ctlds = 0x00000030,
  72. .grp_b1ds = 0x00000030,
  73. .grp_ddrpke = 0x00000000,
  74. .grp_ddrmode = 0x00020000,
  75. .grp_ddr_type = 0x000c0000,
  76. };
  77. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  78. .dram_dqm0 = 0x00000030,
  79. .dram_dqm1 = 0x00000030,
  80. .dram_ras = 0x00000030,
  81. .dram_cas = 0x00000030,
  82. .dram_odt0 = 0x00000030,
  83. .dram_odt1 = 0x00000030,
  84. .dram_sdba2 = 0x00000000,
  85. .dram_sdclk_0 = 0x00000008,
  86. .dram_sdqs0 = 0x00000038,
  87. .dram_sdqs1 = 0x00000030,
  88. .dram_reset = 0x00000030,
  89. };
  90. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  91. .p0_mpwldectrl0 = 0x00070007,
  92. .p0_mpdgctrl0 = 0x41490145,
  93. .p0_mprddlctl = 0x40404546,
  94. .p0_mpwrdlctl = 0x4040524D,
  95. };
  96. struct mx6_ddr_sysinfo ddr_sysinfo = {
  97. .dsize = 0,
  98. .cs_density = 20,
  99. .ncs = 1,
  100. .cs1_mirror = 0,
  101. .rtt_wr = 2,
  102. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  103. .walat = 1, /* Write additional latency */
  104. .ralat = 5, /* Read additional latency */
  105. .mif3_mode = 3, /* Command prediction working mode */
  106. .bi_on = 1, /* Bank interleaving enabled */
  107. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  108. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  109. .ddr_type = DDR_TYPE_DDR3,
  110. .refsel = 1, /* Refresh cycles at 32KHz */
  111. .refr = 7, /* 8 refreshes commands per refresh cycle */
  112. };
  113. static struct mx6_ddr3_cfg mem_ddr = {
  114. .mem_speed = 800,
  115. .density = 2,
  116. .width = 16,
  117. .banks = 8,
  118. .rowaddr = 14,
  119. .coladdr = 10,
  120. .pagesz = 2,
  121. .trcd = 1500,
  122. .trcmin = 5250,
  123. .trasmin = 3750,
  124. };
  125. void board_boot_order(u32 *spl_boot_list)
  126. {
  127. unsigned int bmode = readl(&src_base->sbmr2);
  128. if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
  129. spl_boot_list[0] = BOOT_DEVICE_UART;
  130. else
  131. spl_boot_list[0] = spl_boot_device();
  132. }
  133. static void ccgr_init(void)
  134. {
  135. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  136. writel(0xFFFFFFFF, &ccm->CCGR0);
  137. writel(0xFFFFFFFF, &ccm->CCGR1);
  138. writel(0xFFFFFFFF, &ccm->CCGR2);
  139. writel(0xFFFFFFFF, &ccm->CCGR3);
  140. writel(0xFFFFFFFF, &ccm->CCGR4);
  141. writel(0xFFFFFFFF, &ccm->CCGR5);
  142. writel(0xFFFFFFFF, &ccm->CCGR6);
  143. writel(0xFFFFFFFF, &ccm->CCGR7);
  144. }
  145. static void spl_dram_init(void)
  146. {
  147. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  148. struct fuse_bank *bank = &ocotp->bank[4];
  149. struct fuse_bank4_regs *fuse =
  150. (struct fuse_bank4_regs *)bank->fuse_regs;
  151. int reg = readl(&fuse->gp1);
  152. /* 512MB of RAM */
  153. if (reg & 0x1) {
  154. mem_ddr.density = 4;
  155. mem_ddr.rowaddr = 15;
  156. mem_ddr.trcd = 1375;
  157. mem_ddr.trcmin = 4875;
  158. mem_ddr.trasmin = 3500;
  159. }
  160. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  161. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  162. }
  163. void spl_board_init(void)
  164. {
  165. preloader_console_init();
  166. }
  167. void board_init_f(ulong dummy)
  168. {
  169. ccgr_init();
  170. /* setup AIPS and disable watchdog */
  171. arch_cpu_init();
  172. /* setup GP timer */
  173. timer_init();
  174. /* DDR initialization */
  175. spl_dram_init();
  176. }
  177. #endif /* CONFIG_SPL_BUILD */