lowlevel_init.S 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. */
  7. #include <config.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <generated/asm-offsets.h>
  10. #include <linux/linkage.h>
  11. .section ".text.init", "x"
  12. .macro init_arm_erratum
  13. /* ARM erratum ID #468414 */
  14. mrc 15, 0, r1, c1, c0, 1
  15. orr r1, r1, #(1 << 5) /* enable L1NEON bit */
  16. mcr 15, 0, r1, c1, c0, 1
  17. .endm
  18. /*
  19. * L2CC Cache setup/invalidation/disable
  20. */
  21. .macro init_l2cc
  22. /* explicitly disable L2 cache */
  23. mrc 15, 0, r0, c1, c0, 1
  24. bic r0, r0, #0x2
  25. mcr 15, 0, r0, c1, c0, 1
  26. /* reconfigure L2 cache aux control reg */
  27. ldr r0, =0xC0 | /* tag RAM */ \
  28. 0x4 | /* data RAM */ \
  29. 1 << 24 | /* disable write allocate delay */ \
  30. 1 << 23 | /* disable write allocate combine */ \
  31. 1 << 22 /* disable write allocate */
  32. #if defined(CONFIG_MX51)
  33. ldr r3, [r4, #ROM_SI_REV]
  34. cmp r3, #0x10
  35. /* disable write combine for TO 2 and lower revs */
  36. orrls r0, r0, #1 << 25
  37. #endif
  38. mcr 15, 1, r0, c9, c0, 2
  39. /* enable L2 cache */
  40. mrc 15, 0, r0, c1, c0, 1
  41. orr r0, r0, #2
  42. mcr 15, 0, r0, c1, c0, 1
  43. .endm /* init_l2cc */
  44. /* AIPS setup - Only setup MPROTx registers.
  45. * The PACR default values are good.*/
  46. .macro init_aips
  47. /*
  48. * Set all MPROTx to be non-bufferable, trusted for R/W,
  49. * not forced to user-mode.
  50. */
  51. ldr r0, =AIPS1_BASE_ADDR
  52. ldr r1, =0x77777777
  53. str r1, [r0, #0x0]
  54. str r1, [r0, #0x4]
  55. ldr r0, =AIPS2_BASE_ADDR
  56. str r1, [r0, #0x0]
  57. str r1, [r0, #0x4]
  58. /*
  59. * Clear the on and off peripheral modules Supervisor Protect bit
  60. * for SDMA to access them. Did not change the AIPS control registers
  61. * (offset 0x20) access type
  62. */
  63. .endm /* init_aips */
  64. /* M4IF setup */
  65. .macro init_m4if
  66. #ifdef CONFIG_MX51
  67. /* VPU and IPU given higher priority (0x4)
  68. * IPU accesses with ID=0x1 given highest priority (=0xA)
  69. */
  70. ldr r0, =M4IF_BASE_ADDR
  71. ldr r1, =0x00000203
  72. str r1, [r0, #0x40]
  73. str r4, [r0, #0x44]
  74. ldr r1, =0x00120125
  75. str r1, [r0, #0x9C]
  76. ldr r1, =0x001901A3
  77. str r1, [r0, #0x48]
  78. #endif
  79. .endm /* init_m4if */
  80. .macro setup_pll pll, freq
  81. ldr r0, =\pll
  82. adr r2, W_DP_\freq
  83. bl setup_pll_func
  84. .endm
  85. #define W_DP_OP 0
  86. #define W_DP_MFD 4
  87. #define W_DP_MFN 8
  88. setup_pll_func:
  89. ldr r1, =0x00001232
  90. str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
  91. mov r1, #0x2
  92. str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
  93. ldr r1, [r2, #W_DP_OP]
  94. str r1, [r0, #PLL_DP_OP]
  95. str r1, [r0, #PLL_DP_HFS_OP]
  96. ldr r1, [r2, #W_DP_MFD]
  97. str r1, [r0, #PLL_DP_MFD]
  98. str r1, [r0, #PLL_DP_HFS_MFD]
  99. ldr r1, [r2, #W_DP_MFN]
  100. str r1, [r0, #PLL_DP_MFN]
  101. str r1, [r0, #PLL_DP_HFS_MFN]
  102. ldr r1, =0x00001232
  103. str r1, [r0, #PLL_DP_CTL]
  104. 1: ldr r1, [r0, #PLL_DP_CTL]
  105. ands r1, r1, #0x1
  106. beq 1b
  107. /* r10 saved upper lr */
  108. mov pc, lr
  109. .macro setup_pll_errata pll, freq
  110. ldr r2, =\pll
  111. str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
  112. ldr r1, =0x00001236
  113. str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
  114. 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
  115. ands r1, r1, #0x1
  116. beq 1b
  117. ldr r5, \freq
  118. str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
  119. str r5, [r2, #PLL_DP_HFS_MFN]
  120. mov r1, #0x1
  121. str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
  122. 2: ldr r1, [r2, #PLL_DP_CONFIG]
  123. tst r1, #1
  124. bne 2b
  125. ldr r1, =100 /* Wait at least 4 us */
  126. 3: subs r1, r1, #1
  127. bge 3b
  128. mov r1, #0x2
  129. str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
  130. .endm
  131. .macro init_clock
  132. #if defined (CONFIG_MX51)
  133. ldr r0, =CCM_BASE_ADDR
  134. /* Gate of clocks to the peripherals first */
  135. ldr r1, =0x3FFFFFFF
  136. str r1, [r0, #CLKCTL_CCGR0]
  137. str r4, [r0, #CLKCTL_CCGR1]
  138. str r4, [r0, #CLKCTL_CCGR2]
  139. str r4, [r0, #CLKCTL_CCGR3]
  140. ldr r1, =0x00030000
  141. str r1, [r0, #CLKCTL_CCGR4]
  142. ldr r1, =0x00FFF030
  143. str r1, [r0, #CLKCTL_CCGR5]
  144. ldr r1, =0x00000300
  145. str r1, [r0, #CLKCTL_CCGR6]
  146. /* Disable IPU and HSC dividers */
  147. mov r1, #0x60000
  148. str r1, [r0, #CLKCTL_CCDR]
  149. /* Make sure to switch the DDR away from PLL 1 */
  150. ldr r1, =0x19239145
  151. str r1, [r0, #CLKCTL_CBCDR]
  152. /* make sure divider effective */
  153. 1: ldr r1, [r0, #CLKCTL_CDHIPR]
  154. cmp r1, #0x0
  155. bne 1b
  156. /* Switch ARM to step clock */
  157. mov r1, #0x4
  158. str r1, [r0, #CLKCTL_CCSR]
  159. #if defined(CONFIG_MX51_PLL_ERRATA)
  160. setup_pll PLL1_BASE_ADDR, 864
  161. setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
  162. #else
  163. setup_pll PLL1_BASE_ADDR, 800
  164. #endif
  165. setup_pll PLL3_BASE_ADDR, 665
  166. /* Switch peripheral to PLL 3 */
  167. ldr r0, =CCM_BASE_ADDR
  168. ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
  169. str r1, [r0, #CLKCTL_CBCMR]
  170. ldr r1, =0x13239145
  171. str r1, [r0, #CLKCTL_CBCDR]
  172. setup_pll PLL2_BASE_ADDR, 665
  173. /* Switch peripheral to PLL2 */
  174. ldr r0, =CCM_BASE_ADDR
  175. ldr r1, =0x19239145
  176. str r1, [r0, #CLKCTL_CBCDR]
  177. ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
  178. str r1, [r0, #CLKCTL_CBCMR]
  179. setup_pll PLL3_BASE_ADDR, 216
  180. /* Set the platform clock dividers */
  181. ldr r0, =ARM_BASE_ADDR
  182. ldr r1, =0x00000725
  183. str r1, [r0, #0x14]
  184. ldr r0, =CCM_BASE_ADDR
  185. /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
  186. ldr r3, [r4, #ROM_SI_REV]
  187. cmp r3, #0x10
  188. movls r1, #0x1
  189. movhi r1, #0
  190. str r1, [r0, #CLKCTL_CACRR]
  191. /* Switch ARM back to PLL 1 */
  192. str r4, [r0, #CLKCTL_CCSR]
  193. /* setup the rest */
  194. /* Use lp_apm (24MHz) source for perclk */
  195. ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
  196. str r1, [r0, #CLKCTL_CBCMR]
  197. /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
  198. ldr r1, =CONFIG_SYS_CLKTL_CBCDR
  199. str r1, [r0, #CLKCTL_CBCDR]
  200. /* Restore the default values in the Gate registers */
  201. ldr r1, =0xFFFFFFFF
  202. str r1, [r0, #CLKCTL_CCGR0]
  203. str r1, [r0, #CLKCTL_CCGR1]
  204. str r1, [r0, #CLKCTL_CCGR2]
  205. str r1, [r0, #CLKCTL_CCGR3]
  206. str r1, [r0, #CLKCTL_CCGR4]
  207. str r1, [r0, #CLKCTL_CCGR5]
  208. str r1, [r0, #CLKCTL_CCGR6]
  209. /* Use PLL 2 for UART's, get 66.5MHz from it */
  210. ldr r1, =0xA5A2A020
  211. str r1, [r0, #CLKCTL_CSCMR1]
  212. ldr r1, =0x00C30321
  213. str r1, [r0, #CLKCTL_CSCDR1]
  214. /* make sure divider effective */
  215. 1: ldr r1, [r0, #CLKCTL_CDHIPR]
  216. cmp r1, #0x0
  217. bne 1b
  218. str r4, [r0, #CLKCTL_CCDR]
  219. /* for cko - for ARM div by 8 */
  220. mov r1, #0x000A0000
  221. add r1, r1, #0x00000F0
  222. str r1, [r0, #CLKCTL_CCOSR]
  223. #else /* CONFIG_MX53 */
  224. ldr r0, =CCM_BASE_ADDR
  225. /* Gate of clocks to the peripherals first */
  226. ldr r1, =0x3FFFFFFF
  227. str r1, [r0, #CLKCTL_CCGR0]
  228. str r4, [r0, #CLKCTL_CCGR1]
  229. str r4, [r0, #CLKCTL_CCGR2]
  230. str r4, [r0, #CLKCTL_CCGR3]
  231. str r4, [r0, #CLKCTL_CCGR7]
  232. ldr r1, =0x00030000
  233. str r1, [r0, #CLKCTL_CCGR4]
  234. ldr r1, =0x00FFF030
  235. str r1, [r0, #CLKCTL_CCGR5]
  236. ldr r1, =0x0F00030F
  237. str r1, [r0, #CLKCTL_CCGR6]
  238. /* Switch ARM to step clock */
  239. mov r1, #0x4
  240. str r1, [r0, #CLKCTL_CCSR]
  241. setup_pll PLL1_BASE_ADDR, 800
  242. setup_pll PLL3_BASE_ADDR, 400
  243. /* Switch peripheral to PLL3 */
  244. ldr r0, =CCM_BASE_ADDR
  245. ldr r1, =0x00015154
  246. str r1, [r0, #CLKCTL_CBCMR]
  247. ldr r1, =0x02898945
  248. str r1, [r0, #CLKCTL_CBCDR]
  249. /* make sure change is effective */
  250. 1: ldr r1, [r0, #CLKCTL_CDHIPR]
  251. cmp r1, #0x0
  252. bne 1b
  253. setup_pll PLL2_BASE_ADDR, 400
  254. /* Switch peripheral to PLL2 */
  255. ldr r0, =CCM_BASE_ADDR
  256. ldr r1, =0x00888945
  257. str r1, [r0, #CLKCTL_CBCDR]
  258. ldr r1, =0x00016154
  259. str r1, [r0, #CLKCTL_CBCMR]
  260. /*change uart clk parent to pll2*/
  261. ldr r1, [r0, #CLKCTL_CSCMR1]
  262. and r1, r1, #0xfcffffff
  263. orr r1, r1, #0x01000000
  264. str r1, [r0, #CLKCTL_CSCMR1]
  265. /* make sure change is effective */
  266. 1: ldr r1, [r0, #CLKCTL_CDHIPR]
  267. cmp r1, #0x0
  268. bne 1b
  269. setup_pll PLL3_BASE_ADDR, 216
  270. setup_pll PLL4_BASE_ADDR, 455
  271. /* Set the platform clock dividers */
  272. ldr r0, =ARM_BASE_ADDR
  273. ldr r1, =0x00000124
  274. str r1, [r0, #0x14]
  275. ldr r0, =CCM_BASE_ADDR
  276. mov r1, #0
  277. str r1, [r0, #CLKCTL_CACRR]
  278. /* Switch ARM back to PLL 1. */
  279. mov r1, #0x0
  280. str r1, [r0, #CLKCTL_CCSR]
  281. /* make uart div=6 */
  282. ldr r1, [r0, #CLKCTL_CSCDR1]
  283. and r1, r1, #0xffffffc0
  284. orr r1, r1, #0x0a
  285. str r1, [r0, #CLKCTL_CSCDR1]
  286. /* Restore the default values in the Gate registers */
  287. ldr r1, =0xFFFFFFFF
  288. str r1, [r0, #CLKCTL_CCGR0]
  289. str r1, [r0, #CLKCTL_CCGR1]
  290. str r1, [r0, #CLKCTL_CCGR2]
  291. str r1, [r0, #CLKCTL_CCGR3]
  292. str r1, [r0, #CLKCTL_CCGR4]
  293. str r1, [r0, #CLKCTL_CCGR5]
  294. str r1, [r0, #CLKCTL_CCGR6]
  295. str r1, [r0, #CLKCTL_CCGR7]
  296. mov r1, #0x00000
  297. str r1, [r0, #CLKCTL_CCDR]
  298. /* for cko - for ARM div by 8 */
  299. mov r1, #0x000A0000
  300. add r1, r1, #0x00000F0
  301. str r1, [r0, #CLKCTL_CCOSR]
  302. #endif /* CONFIG_MX53 */
  303. .endm
  304. ENTRY(lowlevel_init)
  305. mov r10, lr
  306. mov r4, #0 /* Fix R4 to 0 */
  307. #if defined(CONFIG_SYS_MAIN_PWR_ON)
  308. ldr r0, =GPIO1_BASE_ADDR
  309. ldr r1, [r0, #0x0]
  310. orr r1, r1, #1 << 23
  311. str r1, [r0, #0x0]
  312. ldr r1, [r0, #0x4]
  313. orr r1, r1, #1 << 23
  314. str r1, [r0, #0x4]
  315. #endif
  316. init_arm_erratum
  317. init_l2cc
  318. init_aips
  319. init_m4if
  320. init_clock
  321. mov pc, r10
  322. ENDPROC(lowlevel_init)
  323. /* Board level setting value */
  324. #if defined(CONFIG_MX51_PLL_ERRATA)
  325. W_DP_864: .word DP_OP_864
  326. .word DP_MFD_864
  327. .word DP_MFN_864
  328. W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
  329. #else
  330. W_DP_800: .word DP_OP_800
  331. .word DP_MFD_800
  332. .word DP_MFN_800
  333. #endif
  334. #if defined(CONFIG_MX51)
  335. W_DP_665: .word DP_OP_665
  336. .word DP_MFD_665
  337. .word DP_MFN_665
  338. #endif
  339. W_DP_216: .word DP_OP_216
  340. .word DP_MFD_216
  341. .word DP_MFN_216
  342. W_DP_400: .word DP_OP_400
  343. .word DP_MFD_400
  344. .word DP_MFN_400
  345. W_DP_455: .word DP_OP_455
  346. .word DP_MFD_455
  347. .word DP_MFN_455