soc.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/hab.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/syscounter.h>
  19. #include <asm/ptrace.h>
  20. #include <asm/armv8/mmu.h>
  21. #include <dm/uclass.h>
  22. #include <efi_loader.h>
  23. #include <env.h>
  24. #include <env_internal.h>
  25. #include <errno.h>
  26. #include <fdt_support.h>
  27. #include <fsl_wdog.h>
  28. #include <imx_sip.h>
  29. #include <linux/arm-smccc.h>
  30. #include <linux/bitops.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #if defined(CONFIG_IMX_HAB)
  33. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  34. .bank = 1,
  35. .word = 3,
  36. };
  37. #endif
  38. int timer_init(void)
  39. {
  40. #ifdef CONFIG_SPL_BUILD
  41. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  42. unsigned long freq = readl(&sctr->cntfid0);
  43. /* Update with accurate clock frequency */
  44. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  45. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  46. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  47. #endif
  48. gd->arch.tbl = 0;
  49. gd->arch.tbu = 0;
  50. return 0;
  51. }
  52. void enable_tzc380(void)
  53. {
  54. struct iomuxc_gpr_base_regs *gpr =
  55. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  56. /* Enable TZASC and lock setting */
  57. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  58. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  59. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  60. setbits_le32(&gpr->gpr[10], BIT(1));
  61. /*
  62. * set Region 0 attribute to allow secure and non-secure
  63. * read/write permission. Found some masters like usb dwc3
  64. * controllers can't work with secure memory.
  65. */
  66. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  67. }
  68. void set_wdog_reset(struct wdog_regs *wdog)
  69. {
  70. /*
  71. * Output WDOG_B signal to reset external pmic or POR_B decided by
  72. * the board design. Without external reset, the peripherals/DDR/
  73. * PMIC are not reset, that may cause system working abnormal.
  74. * WDZST bit is write-once only bit. Align this bit in kernel,
  75. * otherwise kernel code will have no chance to set this bit.
  76. */
  77. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  78. }
  79. static struct mm_region imx8m_mem_map[] = {
  80. {
  81. /* ROM */
  82. .virt = 0x0UL,
  83. .phys = 0x0UL,
  84. .size = 0x100000UL,
  85. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  86. PTE_BLOCK_OUTER_SHARE
  87. }, {
  88. /* CAAM */
  89. .virt = 0x100000UL,
  90. .phys = 0x100000UL,
  91. .size = 0x8000UL,
  92. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  93. PTE_BLOCK_NON_SHARE |
  94. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  95. }, {
  96. /* TCM */
  97. .virt = 0x7C0000UL,
  98. .phys = 0x7C0000UL,
  99. .size = 0x80000UL,
  100. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  101. PTE_BLOCK_NON_SHARE |
  102. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  103. }, {
  104. /* OCRAM */
  105. .virt = 0x900000UL,
  106. .phys = 0x900000UL,
  107. .size = 0x200000UL,
  108. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  109. PTE_BLOCK_OUTER_SHARE
  110. }, {
  111. /* AIPS */
  112. .virt = 0xB00000UL,
  113. .phys = 0xB00000UL,
  114. .size = 0x3f500000UL,
  115. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  116. PTE_BLOCK_NON_SHARE |
  117. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  118. }, {
  119. /* DRAM1 */
  120. .virt = 0x40000000UL,
  121. .phys = 0x40000000UL,
  122. .size = PHYS_SDRAM_SIZE,
  123. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  124. PTE_BLOCK_OUTER_SHARE
  125. #ifdef PHYS_SDRAM_2_SIZE
  126. }, {
  127. /* DRAM2 */
  128. .virt = 0x100000000UL,
  129. .phys = 0x100000000UL,
  130. .size = PHYS_SDRAM_2_SIZE,
  131. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  132. PTE_BLOCK_OUTER_SHARE
  133. #endif
  134. }, {
  135. /* empty entrie to split table entry 5 if needed when TEEs are used */
  136. 0,
  137. }, {
  138. /* List terminator */
  139. 0,
  140. }
  141. };
  142. struct mm_region *mem_map = imx8m_mem_map;
  143. void enable_caches(void)
  144. {
  145. /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
  146. if (rom_pointer[1]) {
  147. /*
  148. * TEE are loaded, So the ddr bank structures
  149. * have been modified update mmu table accordingly
  150. */
  151. int i = 0;
  152. /*
  153. * please make sure that entry initial value matches
  154. * imx8m_mem_map for DRAM1
  155. */
  156. int entry = 5;
  157. u64 attrs = imx8m_mem_map[entry].attrs;
  158. while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
  159. if (gd->bd->bi_dram[i].start == 0)
  160. break;
  161. imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
  162. imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
  163. imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
  164. imx8m_mem_map[entry].attrs = attrs;
  165. debug("Added memory mapping (%d): %llx %llx\n", entry,
  166. imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
  167. i++; entry++;
  168. }
  169. }
  170. icache_enable();
  171. dcache_enable();
  172. }
  173. __weak int board_phys_sdram_size(phys_size_t *size)
  174. {
  175. if (!size)
  176. return -EINVAL;
  177. *size = PHYS_SDRAM_SIZE;
  178. return 0;
  179. }
  180. int dram_init(void)
  181. {
  182. phys_size_t sdram_size;
  183. int ret;
  184. ret = board_phys_sdram_size(&sdram_size);
  185. if (ret)
  186. return ret;
  187. /* rom_pointer[1] contains the size of TEE occupies */
  188. if (rom_pointer[1])
  189. gd->ram_size = sdram_size - rom_pointer[1];
  190. else
  191. gd->ram_size = sdram_size;
  192. /* also update the SDRAM size in the mem_map used externally */
  193. imx8m_mem_map[5].size = sdram_size;
  194. #ifdef PHYS_SDRAM_2_SIZE
  195. gd->ram_size += PHYS_SDRAM_2_SIZE;
  196. #endif
  197. return 0;
  198. }
  199. int dram_init_banksize(void)
  200. {
  201. int bank = 0;
  202. int ret;
  203. phys_size_t sdram_size;
  204. ret = board_phys_sdram_size(&sdram_size);
  205. if (ret)
  206. return ret;
  207. gd->bd->bi_dram[bank].start = PHYS_SDRAM;
  208. if (rom_pointer[1]) {
  209. phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
  210. phys_size_t optee_size = (size_t)rom_pointer[1];
  211. gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
  212. if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
  213. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  214. puts("CONFIG_NR_DRAM_BANKS is not enough\n");
  215. return -1;
  216. }
  217. gd->bd->bi_dram[bank].start = optee_start + optee_size;
  218. gd->bd->bi_dram[bank].size = PHYS_SDRAM +
  219. sdram_size - gd->bd->bi_dram[bank].start;
  220. }
  221. } else {
  222. gd->bd->bi_dram[bank].size = sdram_size;
  223. }
  224. #ifdef PHYS_SDRAM_2_SIZE
  225. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  226. puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
  227. return -1;
  228. }
  229. gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
  230. gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
  231. #endif
  232. return 0;
  233. }
  234. phys_size_t get_effective_memsize(void)
  235. {
  236. /* return the first bank as effective memory */
  237. if (rom_pointer[1])
  238. return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
  239. #ifdef PHYS_SDRAM_2_SIZE
  240. return gd->ram_size - PHYS_SDRAM_2_SIZE;
  241. #else
  242. return gd->ram_size;
  243. #endif
  244. }
  245. static u32 get_cpu_variant_type(u32 type)
  246. {
  247. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  248. struct fuse_bank *bank = &ocotp->bank[1];
  249. struct fuse_bank1_regs *fuse =
  250. (struct fuse_bank1_regs *)bank->fuse_regs;
  251. u32 value = readl(&fuse->tester4);
  252. if (type == MXC_CPU_IMX8MQ) {
  253. if ((value & 0x3) == 0x2)
  254. return MXC_CPU_IMX8MD;
  255. else if (value & 0x200000)
  256. return MXC_CPU_IMX8MQL;
  257. } else if (type == MXC_CPU_IMX8MM) {
  258. switch (value & 0x3) {
  259. case 2:
  260. if (value & 0x1c0000)
  261. return MXC_CPU_IMX8MMDL;
  262. else
  263. return MXC_CPU_IMX8MMD;
  264. case 3:
  265. if (value & 0x1c0000)
  266. return MXC_CPU_IMX8MMSL;
  267. else
  268. return MXC_CPU_IMX8MMS;
  269. default:
  270. if (value & 0x1c0000)
  271. return MXC_CPU_IMX8MML;
  272. break;
  273. }
  274. } else if (type == MXC_CPU_IMX8MN) {
  275. switch (value & 0x3) {
  276. case 2:
  277. if (value & 0x1000000)
  278. return MXC_CPU_IMX8MNDL;
  279. else
  280. return MXC_CPU_IMX8MND;
  281. case 3:
  282. if (value & 0x1000000)
  283. return MXC_CPU_IMX8MNSL;
  284. else
  285. return MXC_CPU_IMX8MNS;
  286. default:
  287. if (value & 0x1000000)
  288. return MXC_CPU_IMX8MNL;
  289. break;
  290. }
  291. } else if (type == MXC_CPU_IMX8MP) {
  292. u32 value0 = readl(&fuse->tester3);
  293. u32 flag = 0;
  294. if ((value0 & 0xc0000) == 0x80000)
  295. return MXC_CPU_IMX8MPD;
  296. /* vpu disabled */
  297. if ((value0 & 0x43000000) == 0x43000000)
  298. flag = 1;
  299. /* npu disabled*/
  300. if ((value & 0x8) == 0x8)
  301. flag |= (1 << 1);
  302. /* isp disabled */
  303. if ((value & 0x3) == 0x3)
  304. flag |= (1 << 2);
  305. switch (flag) {
  306. case 7:
  307. return MXC_CPU_IMX8MPL;
  308. case 2:
  309. return MXC_CPU_IMX8MP6;
  310. default:
  311. break;
  312. }
  313. }
  314. return type;
  315. }
  316. u32 get_cpu_rev(void)
  317. {
  318. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  319. u32 reg = readl(&ana_pll->digprog);
  320. u32 type = (reg >> 16) & 0xff;
  321. u32 major_low = (reg >> 8) & 0xff;
  322. u32 rom_version;
  323. reg &= 0xff;
  324. /* iMX8MP */
  325. if (major_low == 0x43) {
  326. type = get_cpu_variant_type(MXC_CPU_IMX8MP);
  327. } else if (major_low == 0x42) {
  328. /* iMX8MN */
  329. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  330. } else if (major_low == 0x41) {
  331. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  332. } else {
  333. if (reg == CHIP_REV_1_0) {
  334. /*
  335. * For B0 chip, the DIGPROG is not updated,
  336. * it is still TO1.0. we have to check ROM
  337. * version or OCOTP_READ_FUSE_DATA.
  338. * 0xff0055aa is magic number for B1.
  339. */
  340. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  341. reg = CHIP_REV_2_1;
  342. } else {
  343. rom_version =
  344. readl((void __iomem *)ROM_VERSION_A0);
  345. if (rom_version != CHIP_REV_1_0) {
  346. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  347. rom_version &= 0xff;
  348. if (rom_version == CHIP_REV_2_0)
  349. reg = CHIP_REV_2_0;
  350. }
  351. }
  352. }
  353. type = get_cpu_variant_type(type);
  354. }
  355. return (type << 12) | reg;
  356. }
  357. static void imx_set_wdog_powerdown(bool enable)
  358. {
  359. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  360. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  361. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  362. /* Write to the PDE (Power Down Enable) bit */
  363. writew(enable, &wdog1->wmcr);
  364. writew(enable, &wdog2->wmcr);
  365. writew(enable, &wdog3->wmcr);
  366. }
  367. int arch_cpu_init_dm(void)
  368. {
  369. struct udevice *dev;
  370. int ret;
  371. if (CONFIG_IS_ENABLED(CLK)) {
  372. ret = uclass_get_device_by_name(UCLASS_CLK,
  373. "clock-controller@30380000",
  374. &dev);
  375. if (ret < 0) {
  376. printf("Failed to find clock node. Check device tree\n");
  377. return ret;
  378. }
  379. }
  380. return 0;
  381. }
  382. int arch_cpu_init(void)
  383. {
  384. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  385. /*
  386. * ROM might disable clock for SCTR,
  387. * enable the clock before timer_init.
  388. */
  389. if (IS_ENABLED(CONFIG_SPL_BUILD))
  390. clock_enable(CCGR_SCTR, 1);
  391. /*
  392. * Init timer at very early state, because sscg pll setting
  393. * will use it
  394. */
  395. timer_init();
  396. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  397. clock_init();
  398. imx_set_wdog_powerdown(false);
  399. if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
  400. is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
  401. is_imx8mnsl() || is_imx8mpd()) {
  402. /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
  403. struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
  404. struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
  405. struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
  406. struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
  407. writel(0x1, &pgc_core2->pgcr);
  408. writel(0x1, &pgc_core3->pgcr);
  409. if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
  410. writel(0x1, &pgc_core1->pgcr);
  411. writel(0xE, &gpc->cpu_pgc_dn_trg);
  412. } else {
  413. writel(0xC, &gpc->cpu_pgc_dn_trg);
  414. }
  415. }
  416. }
  417. if (is_imx8mq()) {
  418. clock_enable(CCGR_OCOTP, 1);
  419. if (readl(&ocotp->ctrl) & 0x200)
  420. writel(0x200, &ocotp->ctrl_clr);
  421. }
  422. return 0;
  423. }
  424. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  425. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  426. enum boot_device get_boot_device(void)
  427. {
  428. volatile gd_t *pgd = gd;
  429. int ret;
  430. u32 boot;
  431. u16 boot_type;
  432. u8 boot_instance;
  433. enum boot_device boot_dev = SD1_BOOT;
  434. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  435. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  436. gd = pgd;
  437. if (ret != ROM_API_OKAY) {
  438. puts("ROMAPI: failure at query_boot_info\n");
  439. return -1;
  440. }
  441. boot_type = boot >> 16;
  442. boot_instance = (boot >> 8) & 0xff;
  443. switch (boot_type) {
  444. case BT_DEV_TYPE_SD:
  445. boot_dev = boot_instance + SD1_BOOT;
  446. break;
  447. case BT_DEV_TYPE_MMC:
  448. boot_dev = boot_instance + MMC1_BOOT;
  449. break;
  450. case BT_DEV_TYPE_NAND:
  451. boot_dev = NAND_BOOT;
  452. break;
  453. case BT_DEV_TYPE_FLEXSPINOR:
  454. boot_dev = QSPI_BOOT;
  455. break;
  456. case BT_DEV_TYPE_USB:
  457. boot_dev = USB_BOOT;
  458. break;
  459. default:
  460. break;
  461. }
  462. return boot_dev;
  463. }
  464. #endif
  465. bool is_usb_boot(void)
  466. {
  467. return get_boot_device() == USB_BOOT;
  468. }
  469. #ifdef CONFIG_OF_SYSTEM_SETUP
  470. bool check_fdt_new_path(void *blob)
  471. {
  472. const char *soc_path = "/soc@0";
  473. int nodeoff;
  474. nodeoff = fdt_path_offset(blob, soc_path);
  475. if (nodeoff < 0)
  476. return false;
  477. return true;
  478. }
  479. static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
  480. {
  481. int i = 0;
  482. int rc;
  483. int nodeoff;
  484. const char *status = "disabled";
  485. for (i = 0; i < size_array; i++) {
  486. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  487. if (nodeoff < 0)
  488. continue; /* Not found, skip it */
  489. printf("Found %s node\n", nodes_path[i]);
  490. add_status:
  491. rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
  492. if (rc) {
  493. if (rc == -FDT_ERR_NOSPACE) {
  494. rc = fdt_increase_size(blob, 512);
  495. if (!rc)
  496. goto add_status;
  497. }
  498. printf("Unable to update property %s:%s, err=%s\n",
  499. nodes_path[i], "status", fdt_strerror(rc));
  500. } else {
  501. printf("Modify %s:%s disabled\n",
  502. nodes_path[i], "status");
  503. }
  504. }
  505. return 0;
  506. }
  507. #ifdef CONFIG_IMX8MQ
  508. bool check_dcss_fused(void)
  509. {
  510. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  511. struct fuse_bank *bank = &ocotp->bank[1];
  512. struct fuse_bank1_regs *fuse =
  513. (struct fuse_bank1_regs *)bank->fuse_regs;
  514. u32 value = readl(&fuse->tester4);
  515. if (value & 0x4000000)
  516. return true;
  517. return false;
  518. }
  519. static int disable_mipi_dsi_nodes(void *blob)
  520. {
  521. static const char * const nodes_path[] = {
  522. "/mipi_dsi@30A00000",
  523. "/mipi_dsi_bridge@30A00000",
  524. "/dsi_phy@30A00300",
  525. "/soc@0/bus@30800000/mipi_dsi@30a00000",
  526. "/soc@0/bus@30800000/dphy@30a00300"
  527. };
  528. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  529. }
  530. static int disable_dcss_nodes(void *blob)
  531. {
  532. static const char * const nodes_path[] = {
  533. "/dcss@0x32e00000",
  534. "/dcss@32e00000",
  535. "/hdmi@32c00000",
  536. "/hdmi_cec@32c33800",
  537. "/hdmi_drm@32c00000",
  538. "/display-subsystem",
  539. "/sound-hdmi",
  540. "/sound-hdmi-arc",
  541. "/soc@0/bus@32c00000/display-controller@32e00000",
  542. "/soc@0/bus@32c00000/hdmi@32c00000",
  543. };
  544. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  545. }
  546. static int check_mipi_dsi_nodes(void *blob)
  547. {
  548. static const char * const lcdif_path[] = {
  549. "/lcdif@30320000",
  550. "/soc@0/bus@30000000/lcdif@30320000"
  551. };
  552. static const char * const mipi_dsi_path[] = {
  553. "/mipi_dsi@30A00000",
  554. "/soc@0/bus@30800000/mipi_dsi@30a00000"
  555. };
  556. static const char * const lcdif_ep_path[] = {
  557. "/lcdif@30320000/port@0/mipi-dsi-endpoint",
  558. "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint"
  559. };
  560. static const char * const mipi_dsi_ep_path[] = {
  561. "/mipi_dsi@30A00000/port@1/endpoint",
  562. "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint"
  563. };
  564. int lookup_node;
  565. int nodeoff;
  566. bool new_path = check_fdt_new_path(blob);
  567. int i = new_path ? 1 : 0;
  568. nodeoff = fdt_path_offset(blob, lcdif_path[i]);
  569. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
  570. /*
  571. * If can't find lcdif node or lcdif node is disabled,
  572. * then disable all mipi dsi, since they only can input
  573. * from DCSS
  574. */
  575. return disable_mipi_dsi_nodes(blob);
  576. }
  577. nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
  578. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
  579. return 0;
  580. nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
  581. if (nodeoff < 0) {
  582. /*
  583. * If can't find lcdif endpoint, then disable all mipi dsi,
  584. * since they only can input from DCSS
  585. */
  586. return disable_mipi_dsi_nodes(blob);
  587. }
  588. lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
  589. nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
  590. if (nodeoff > 0 && nodeoff == lookup_node)
  591. return 0;
  592. return disable_mipi_dsi_nodes(blob);
  593. }
  594. #endif
  595. int disable_vpu_nodes(void *blob)
  596. {
  597. static const char * const nodes_path_8mq[] = {
  598. "/vpu@38300000",
  599. "/soc@0/vpu@38300000"
  600. };
  601. static const char * const nodes_path_8mm[] = {
  602. "/vpu_g1@38300000",
  603. "/vpu_g2@38310000",
  604. "/vpu_h1@38320000"
  605. };
  606. static const char * const nodes_path_8mp[] = {
  607. "/vpu_g1@38300000",
  608. "/vpu_g2@38310000",
  609. "/vpu_vc8000e@38320000"
  610. };
  611. if (is_imx8mq())
  612. return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
  613. else if (is_imx8mm())
  614. return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
  615. else if (is_imx8mp())
  616. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  617. else
  618. return -EPERM;
  619. }
  620. int disable_gpu_nodes(void *blob)
  621. {
  622. static const char * const nodes_path_8mn[] = {
  623. "/gpu@38000000"
  624. };
  625. return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
  626. }
  627. int disable_npu_nodes(void *blob)
  628. {
  629. static const char * const nodes_path_8mp[] = {
  630. "/vipsi@38500000"
  631. };
  632. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  633. }
  634. int disable_isp_nodes(void *blob)
  635. {
  636. static const char * const nodes_path_8mp[] = {
  637. "/soc@0/bus@32c00000/camera/isp@32e10000",
  638. "/soc@0/bus@32c00000/camera/isp@32e20000"
  639. };
  640. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  641. }
  642. int disable_dsp_nodes(void *blob)
  643. {
  644. static const char * const nodes_path_8mp[] = {
  645. "/dsp@3b6e8000"
  646. };
  647. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  648. }
  649. static int disable_cpu_nodes(void *blob, u32 disabled_cores)
  650. {
  651. static const char * const nodes_path[] = {
  652. "/cpus/cpu@1",
  653. "/cpus/cpu@2",
  654. "/cpus/cpu@3",
  655. };
  656. u32 i = 0;
  657. int rc;
  658. int nodeoff;
  659. if (disabled_cores > 3)
  660. return -EINVAL;
  661. i = 3 - disabled_cores;
  662. for (; i < 3; i++) {
  663. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  664. if (nodeoff < 0)
  665. continue; /* Not found, skip it */
  666. debug("Found %s node\n", nodes_path[i]);
  667. rc = fdt_del_node(blob, nodeoff);
  668. if (rc < 0) {
  669. printf("Unable to delete node %s, err=%s\n",
  670. nodes_path[i], fdt_strerror(rc));
  671. } else {
  672. printf("Delete node %s\n", nodes_path[i]);
  673. }
  674. }
  675. return 0;
  676. }
  677. int ft_system_setup(void *blob, struct bd_info *bd)
  678. {
  679. #ifdef CONFIG_IMX8MQ
  680. int i = 0;
  681. int rc;
  682. int nodeoff;
  683. if (get_boot_device() == USB_BOOT) {
  684. disable_dcss_nodes(blob);
  685. bool new_path = check_fdt_new_path(blob);
  686. int v = new_path ? 1 : 0;
  687. static const char * const usb_dwc3_path[] = {
  688. "/usb@38100000/dwc3",
  689. "/soc@0/usb@38100000"
  690. };
  691. nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
  692. if (nodeoff >= 0) {
  693. const char *speed = "high-speed";
  694. printf("Found %s node\n", usb_dwc3_path[v]);
  695. usb_modify_speed:
  696. rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
  697. if (rc) {
  698. if (rc == -FDT_ERR_NOSPACE) {
  699. rc = fdt_increase_size(blob, 512);
  700. if (!rc)
  701. goto usb_modify_speed;
  702. }
  703. printf("Unable to set property %s:%s, err=%s\n",
  704. usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
  705. } else {
  706. printf("Modify %s:%s = %s\n",
  707. usb_dwc3_path[v], "maximum-speed", speed);
  708. }
  709. } else {
  710. printf("Can't found %s node\n", usb_dwc3_path[v]);
  711. }
  712. }
  713. /* Disable the CPU idle for A0 chip since the HW does not support it */
  714. if (is_soc_rev(CHIP_REV_1_0)) {
  715. static const char * const nodes_path[] = {
  716. "/cpus/cpu@0",
  717. "/cpus/cpu@1",
  718. "/cpus/cpu@2",
  719. "/cpus/cpu@3",
  720. };
  721. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  722. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  723. if (nodeoff < 0)
  724. continue; /* Not found, skip it */
  725. debug("Found %s node\n", nodes_path[i]);
  726. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  727. if (rc == -FDT_ERR_NOTFOUND)
  728. continue;
  729. if (rc) {
  730. printf("Unable to update property %s:%s, err=%s\n",
  731. nodes_path[i], "status", fdt_strerror(rc));
  732. return rc;
  733. }
  734. debug("Remove %s:%s\n", nodes_path[i],
  735. "cpu-idle-states");
  736. }
  737. }
  738. if (is_imx8mql()) {
  739. disable_vpu_nodes(blob);
  740. if (check_dcss_fused()) {
  741. printf("DCSS is fused\n");
  742. disable_dcss_nodes(blob);
  743. check_mipi_dsi_nodes(blob);
  744. }
  745. }
  746. if (is_imx8md())
  747. disable_cpu_nodes(blob, 2);
  748. #elif defined(CONFIG_IMX8MM)
  749. if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
  750. disable_vpu_nodes(blob);
  751. if (is_imx8mmd() || is_imx8mmdl())
  752. disable_cpu_nodes(blob, 2);
  753. else if (is_imx8mms() || is_imx8mmsl())
  754. disable_cpu_nodes(blob, 3);
  755. #elif defined(CONFIG_IMX8MN)
  756. if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
  757. disable_gpu_nodes(blob);
  758. if (is_imx8mnd() || is_imx8mndl())
  759. disable_cpu_nodes(blob, 2);
  760. else if (is_imx8mns() || is_imx8mnsl())
  761. disable_cpu_nodes(blob, 3);
  762. #elif defined(CONFIG_IMX8MP)
  763. if (is_imx8mpl())
  764. disable_vpu_nodes(blob);
  765. if (is_imx8mpl() || is_imx8mp6())
  766. disable_npu_nodes(blob);
  767. if (is_imx8mpl())
  768. disable_isp_nodes(blob);
  769. if (is_imx8mpl() || is_imx8mp6())
  770. disable_dsp_nodes(blob);
  771. if (is_imx8mpd())
  772. disable_cpu_nodes(blob, 2);
  773. #endif
  774. return 0;
  775. }
  776. #endif
  777. #if !CONFIG_IS_ENABLED(SYSRESET)
  778. void reset_cpu(ulong addr)
  779. {
  780. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  781. /* Clear WDA to trigger WDOG_B immediately */
  782. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  783. while (1) {
  784. /*
  785. * spin for .5 seconds before reset
  786. */
  787. }
  788. }
  789. #endif
  790. #if defined(CONFIG_ARCH_MISC_INIT)
  791. static void acquire_buildinfo(void)
  792. {
  793. u64 atf_commit = 0;
  794. struct arm_smccc_res res;
  795. /* Get ARM Trusted Firmware commit id */
  796. arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
  797. 0, 0, 0, 0, 0, 0, &res);
  798. atf_commit = res.a0;
  799. if (atf_commit == 0xffffffff) {
  800. debug("ATF does not support build info\n");
  801. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  802. }
  803. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  804. }
  805. int arch_misc_init(void)
  806. {
  807. acquire_buildinfo();
  808. return 0;
  809. }
  810. #endif
  811. void imx_tmu_arch_init(void *reg_base)
  812. {
  813. if (is_imx8mm() || is_imx8mn()) {
  814. /* Load TCALIV and TASR from fuses */
  815. struct ocotp_regs *ocotp =
  816. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  817. struct fuse_bank *bank = &ocotp->bank[3];
  818. struct fuse_bank3_regs *fuse =
  819. (struct fuse_bank3_regs *)bank->fuse_regs;
  820. u32 tca_rt, tca_hr, tca_en;
  821. u32 buf_vref, buf_slope;
  822. tca_rt = fuse->ana0 & 0xFF;
  823. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  824. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  825. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  826. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  827. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  828. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  829. (ulong)reg_base + 0x30);
  830. }
  831. #ifdef CONFIG_IMX8MP
  832. /* Load TCALIV0/1/m40 and TRIM from fuses */
  833. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  834. struct fuse_bank *bank = &ocotp->bank[38];
  835. struct fuse_bank38_regs *fuse =
  836. (struct fuse_bank38_regs *)bank->fuse_regs;
  837. struct fuse_bank *bank2 = &ocotp->bank[39];
  838. struct fuse_bank39_regs *fuse2 =
  839. (struct fuse_bank39_regs *)bank2->fuse_regs;
  840. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  841. u32 reg;
  842. u32 tca40[2], tca25[2], tca105[2];
  843. /* For blank sample */
  844. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  845. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  846. /* Use a default 25C binary codes */
  847. tca25[0] = 1596;
  848. tca25[1] = 1596;
  849. writel(tca25[0], (ulong)reg_base + 0x30);
  850. writel(tca25[1], (ulong)reg_base + 0x34);
  851. return;
  852. }
  853. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  854. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  855. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  856. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  857. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  858. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  859. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  860. writel(reg, (ulong)reg_base + 0x3c);
  861. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  862. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  863. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  864. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  865. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  866. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  867. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  868. /* use 25c for 1p calibration */
  869. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  870. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  871. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  872. #endif
  873. }
  874. #if defined(CONFIG_SPL_BUILD)
  875. #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
  876. bool serror_need_skip = true;
  877. void do_error(struct pt_regs *pt_regs, unsigned int esr)
  878. {
  879. /*
  880. * If stack is still in ROM reserved OCRAM not switch to SPL,
  881. * it is the ROM SError
  882. */
  883. ulong sp;
  884. asm volatile("mov %0, sp" : "=r"(sp) : );
  885. if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
  886. /* Check for ERR050342, imx8mq HDCP enabled parts */
  887. if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
  888. serror_need_skip = false;
  889. return; /* Do nothing skip the SError in ROM */
  890. }
  891. /* Check for ERR050350, field return mode for imx8mq, mm and mn */
  892. if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
  893. serror_need_skip = false;
  894. return; /* Do nothing skip the SError in ROM */
  895. }
  896. }
  897. efi_restore_gd();
  898. printf("\"Error\" handler, esr 0x%08x\n", esr);
  899. show_regs(pt_regs);
  900. panic("Resetting CPU ...\n");
  901. }
  902. #endif
  903. #endif
  904. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  905. enum env_location env_get_location(enum env_operation op, int prio)
  906. {
  907. enum boot_device dev = get_boot_device();
  908. enum env_location env_loc = ENVL_UNKNOWN;
  909. if (prio)
  910. return env_loc;
  911. switch (dev) {
  912. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  913. case QSPI_BOOT:
  914. env_loc = ENVL_SPI_FLASH;
  915. break;
  916. #endif
  917. #ifdef CONFIG_ENV_IS_IN_NAND
  918. case NAND_BOOT:
  919. env_loc = ENVL_NAND;
  920. break;
  921. #endif
  922. #ifdef CONFIG_ENV_IS_IN_MMC
  923. case SD1_BOOT:
  924. case SD2_BOOT:
  925. case SD3_BOOT:
  926. case MMC1_BOOT:
  927. case MMC2_BOOT:
  928. case MMC3_BOOT:
  929. env_loc = ENVL_MMC;
  930. break;
  931. #endif
  932. default:
  933. #if defined(CONFIG_ENV_IS_NOWHERE)
  934. env_loc = ENVL_NOWHERE;
  935. #endif
  936. break;
  937. }
  938. return env_loc;
  939. }
  940. #ifndef ENV_IS_EMBEDDED
  941. long long env_get_offset(long long defautl_offset)
  942. {
  943. enum boot_device dev = get_boot_device();
  944. switch (dev) {
  945. case NAND_BOOT:
  946. return (60 << 20); /* 60MB offset for NAND */
  947. default:
  948. break;
  949. }
  950. return defautl_offset;
  951. }
  952. #endif
  953. #endif