spl_boot.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/global_data.h>
  10. #include <asm/cache.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/dmc.h>
  14. #include <asm/arch/periph.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <asm/arch/power.h>
  17. #include <asm/arch/spl.h>
  18. #include <asm/arch/spi.h>
  19. #include "common_setup.h"
  20. #include "clock_init.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* Index into irom ptr table */
  23. enum index {
  24. MMC_INDEX,
  25. EMMC44_INDEX,
  26. EMMC44_END_INDEX,
  27. SPI_INDEX,
  28. USB_INDEX,
  29. };
  30. /* IROM Function Pointers Table */
  31. u32 irom_ptr_table[] = {
  32. [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
  33. [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
  34. [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
  35. -EMMC4.4 end boot operation */
  36. [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
  37. [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
  38. };
  39. void *get_irom_func(int index)
  40. {
  41. return (void *)*(u32 *)irom_ptr_table[index];
  42. }
  43. #ifdef CONFIG_USB_BOOTING
  44. /*
  45. * Set/clear program flow prediction and return the previous state.
  46. */
  47. static int config_branch_prediction(int set_cr_z)
  48. {
  49. unsigned int cr;
  50. /* System Control Register: 11th bit Z Branch prediction enable */
  51. cr = get_cr();
  52. set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
  53. return cr & CR_Z;
  54. }
  55. #endif
  56. #ifdef CONFIG_SPI_BOOTING
  57. static void spi_rx_tx(struct exynos_spi *regs, int todo,
  58. void *dinp, void const *doutp, int i)
  59. {
  60. uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  61. int rx_lvl, tx_lvl;
  62. uint out_bytes, in_bytes;
  63. out_bytes = todo;
  64. in_bytes = todo;
  65. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  66. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  67. writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  68. while (in_bytes) {
  69. uint32_t spi_sts;
  70. int temp;
  71. spi_sts = readl(&regs->spi_sts);
  72. rx_lvl = ((spi_sts >> 15) & 0x7f);
  73. tx_lvl = ((spi_sts >> 6) & 0x7f);
  74. while (tx_lvl < 32 && out_bytes) {
  75. temp = 0xffffffff;
  76. writel(temp, &regs->tx_data);
  77. out_bytes -= 4;
  78. tx_lvl += 4;
  79. }
  80. while (rx_lvl >= 4 && in_bytes) {
  81. temp = readl(&regs->rx_data);
  82. if (rxp)
  83. *rxp++ = temp;
  84. in_bytes -= 4;
  85. rx_lvl -= 4;
  86. }
  87. }
  88. }
  89. /*
  90. * Copy uboot from spi flash to RAM
  91. *
  92. * @parma uboot_size size of u-boot to copy
  93. * @param uboot_addr address in u-boot to copy
  94. */
  95. static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  96. {
  97. int upto, todo;
  98. int i, timeout = 100;
  99. struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
  100. set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  101. /* set the spi1 GPIO */
  102. exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  103. /* set pktcnt and enable it */
  104. writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  105. /* set FB_CLK_SEL */
  106. writel(SPI_FB_DELAY_180, &regs->fb_clk);
  107. /* set CH_WIDTH and BUS_WIDTH as word */
  108. setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  109. SPI_MODE_BUS_WIDTH_WORD);
  110. clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  111. /* clear rx and tx channel if set priveously */
  112. clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  113. setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  114. SPI_RX_BYTE_SWAP |
  115. SPI_RX_HWORD_SWAP);
  116. /* do a soft reset */
  117. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  118. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  119. /* now set rx and tx channel ON */
  120. setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  121. clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  122. /* Send read instruction (0x3h) followed by a 24 bit addr */
  123. writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  124. /* waiting for TX done */
  125. while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  126. if (!timeout) {
  127. debug("SPI TIMEOUT\n");
  128. break;
  129. }
  130. timeout--;
  131. }
  132. for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  133. todo = min(uboot_size - upto, (unsigned int)(1 << 15));
  134. spi_rx_tx(regs, todo, (void *)(uboot_addr),
  135. (void *)(SPI_FLASH_UBOOT_POS), i);
  136. }
  137. setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  138. /*
  139. * Let put controller mode to BYTE as
  140. * SPI driver does not support WORD mode yet
  141. */
  142. clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  143. SPI_MODE_BUS_WIDTH_WORD);
  144. writel(0, &regs->swap_cfg);
  145. /*
  146. * Flush spi tx, rx fifos and reset the SPI controller
  147. * and clear rx/tx channel
  148. */
  149. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  150. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  151. clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  152. }
  153. #endif
  154. /*
  155. * Copy U-Boot from mmc to RAM:
  156. * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
  157. * Pointer to API (Data transfer from mmc to ram)
  158. */
  159. void copy_uboot_to_ram(void)
  160. {
  161. unsigned int bootmode = BOOT_MODE_OM;
  162. u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  163. u32 offset = 0, size = 0;
  164. #ifdef CONFIG_SPI_BOOTING
  165. struct spl_machine_param *param = spl_get_machine_params();
  166. #endif
  167. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  168. u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
  169. void (*end_bootop_from_emmc)(void);
  170. #endif
  171. #ifdef CONFIG_USB_BOOTING
  172. int is_cr_z_set;
  173. unsigned int sec_boot_check;
  174. /*
  175. * Note that older hardware (before Exynos5800) does not expect any
  176. * arguments, but it does not hurt to pass them, so a common function
  177. * prototype is used.
  178. */
  179. u32 (*usb_copy)(u32 num_of_block, u32 *dst);
  180. /* Read iRAM location to check for secondary USB boot mode */
  181. sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  182. if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
  183. bootmode = BOOT_MODE_USB;
  184. #endif
  185. if (bootmode == BOOT_MODE_OM)
  186. bootmode = get_boot_mode();
  187. switch (bootmode) {
  188. #ifdef CONFIG_SPI_BOOTING
  189. case BOOT_MODE_SERIAL:
  190. /* Customised function to copy u-boot from SF */
  191. exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
  192. break;
  193. #endif
  194. case BOOT_MODE_SD:
  195. offset = BL2_START_OFFSET;
  196. size = BL2_SIZE_BLOC_COUNT;
  197. copy_bl2 = get_irom_func(MMC_INDEX);
  198. break;
  199. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  200. case BOOT_MODE_EMMC:
  201. /* Set the FSYS1 clock divisor value for EMMC boot */
  202. emmc_boot_clk_div_set();
  203. copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
  204. end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
  205. copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
  206. end_bootop_from_emmc();
  207. break;
  208. #endif
  209. #ifdef CONFIG_USB_BOOTING
  210. case BOOT_MODE_USB:
  211. /*
  212. * iROM needs program flow prediction to be disabled
  213. * before copy from USB device to RAM
  214. */
  215. is_cr_z_set = config_branch_prediction(0);
  216. usb_copy = get_irom_func(USB_INDEX);
  217. usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
  218. config_branch_prediction(is_cr_z_set);
  219. break;
  220. #endif
  221. default:
  222. break;
  223. }
  224. if (copy_bl2)
  225. copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
  226. }
  227. void memzero(void *s, size_t n)
  228. {
  229. char *ptr = s;
  230. size_t i;
  231. for (i = 0; i < n; i++)
  232. *ptr++ = '\0';
  233. }
  234. /**
  235. * Set up the U-Boot global_data pointer
  236. *
  237. * This sets the address of the global data, and sets up basic values.
  238. *
  239. * @param gdp Value to give to gd
  240. */
  241. static void setup_global_data(gd_t *gdp)
  242. {
  243. gd = gdp;
  244. memzero((void *)gd, sizeof(gd_t));
  245. gd->flags |= GD_FLG_RELOC;
  246. gd->baudrate = CONFIG_BAUDRATE;
  247. gd->have_console = 1;
  248. }
  249. void board_init_f(unsigned long bootflag)
  250. {
  251. __aligned(8) gd_t local_gd;
  252. __attribute__((noreturn)) void (*uboot)(void);
  253. setup_global_data(&local_gd);
  254. if (do_lowlevel_init())
  255. power_exit_wakeup();
  256. copy_uboot_to_ram();
  257. /* Jump to U-Boot image */
  258. uboot = (void *)CONFIG_SYS_TEXT_BASE;
  259. (*uboot)();
  260. /* Never returns Here */
  261. }
  262. /* Place Holders */
  263. void board_init_r(gd_t *id, ulong dest_addr)
  264. {
  265. /* Function attribute is no-return */
  266. /* This Function never executes */
  267. while (1)
  268. ;
  269. }