cpu.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004 Texas Instruments.
  4. * Copyright (C) 2009 David Brownell
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/arch/hardware.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /* offsets from PLL controller base */
  13. #define PLLC_PLLCTL 0x100
  14. #define PLLC_PLLM 0x110
  15. #define PLLC_PREDIV 0x114
  16. #define PLLC_PLLDIV1 0x118
  17. #define PLLC_PLLDIV2 0x11c
  18. #define PLLC_PLLDIV3 0x120
  19. #define PLLC_POSTDIV 0x128
  20. #define PLLC_BPDIV 0x12c
  21. #define PLLC_PLLDIV4 0x160
  22. #define PLLC_PLLDIV5 0x164
  23. #define PLLC_PLLDIV6 0x168
  24. #define PLLC_PLLDIV7 0x16c
  25. #define PLLC_PLLDIV8 0x170
  26. #define PLLC_PLLDIV9 0x174
  27. unsigned int sysdiv[9] = {
  28. PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
  29. PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
  30. };
  31. int clk_get(enum davinci_clk_ids id)
  32. {
  33. int pre_div;
  34. int pllm;
  35. int post_div;
  36. int pll_out;
  37. unsigned int pll_base;
  38. pll_out = CONFIG_SYS_OSCIN_FREQ;
  39. if (id == DAVINCI_AUXCLK_CLKID)
  40. goto out;
  41. if ((id >> 16) == 1)
  42. pll_base = (unsigned int)davinci_pllc1_regs;
  43. else
  44. pll_base = (unsigned int)davinci_pllc0_regs;
  45. id &= 0xFFFF;
  46. /*
  47. * Lets keep this simple. Combining operations can result in
  48. * unexpected approximations
  49. */
  50. pre_div = (readl(pll_base + PLLC_PREDIV) &
  51. DAVINCI_PLLC_DIV_MASK) + 1;
  52. pllm = readl(pll_base + PLLC_PLLM) + 1;
  53. pll_out /= pre_div;
  54. pll_out *= pllm;
  55. if (id == DAVINCI_PLLM_CLKID)
  56. goto out;
  57. post_div = (readl(pll_base + PLLC_POSTDIV) &
  58. DAVINCI_PLLC_DIV_MASK) + 1;
  59. pll_out /= post_div;
  60. if (id == DAVINCI_PLLC_CLKID)
  61. goto out;
  62. pll_out /= (readl(pll_base + sysdiv[id - 1]) &
  63. DAVINCI_PLLC_DIV_MASK) + 1;
  64. out:
  65. return pll_out;
  66. }
  67. int set_cpu_clk_info(void)
  68. {
  69. gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
  70. /* DDR PHY uses an x2 input clock */
  71. gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
  72. (clk_get(DAVINCI_DDR_CLKID) / 1000000);
  73. gd->bd->bi_dsp_freq = 0;
  74. return 0;
  75. }