init.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2012 Stephen Warren
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <dm/device.h>
  12. #include <fdt_support.h>
  13. #include <asm/global_data.h>
  14. #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
  15. #define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
  16. #ifdef CONFIG_ARM64
  17. #include <asm/armv8/mmu.h>
  18. #define MEM_MAP_MAX_ENTRIES (4)
  19. static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
  20. {
  21. .virt = 0x00000000UL,
  22. .phys = 0x00000000UL,
  23. .size = 0x3f000000UL,
  24. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25. PTE_BLOCK_INNER_SHARE
  26. }, {
  27. .virt = 0x3f000000UL,
  28. .phys = 0x3f000000UL,
  29. .size = 0x01000000UL,
  30. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  31. PTE_BLOCK_NON_SHARE |
  32. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  33. }, {
  34. /* List terminator */
  35. 0,
  36. }
  37. };
  38. static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
  39. {
  40. .virt = 0x00000000UL,
  41. .phys = 0x00000000UL,
  42. .size = 0xfc000000UL,
  43. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  44. PTE_BLOCK_INNER_SHARE
  45. }, {
  46. .virt = 0xfc000000UL,
  47. .phys = 0xfc000000UL,
  48. .size = 0x03800000UL,
  49. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50. PTE_BLOCK_NON_SHARE |
  51. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  52. }, {
  53. .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  54. .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  55. .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
  56. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  57. PTE_BLOCK_NON_SHARE |
  58. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  59. }, {
  60. /* List terminator */
  61. 0,
  62. }
  63. };
  64. struct mm_region *mem_map = bcm283x_mem_map;
  65. /*
  66. * I/O address space varies on different chip versions.
  67. * We set the base address by inspecting the DTB.
  68. */
  69. static const struct udevice_id board_ids[] = {
  70. { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
  71. { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
  72. { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
  73. { },
  74. };
  75. static void _rpi_update_mem_map(struct mm_region *pd)
  76. {
  77. int i;
  78. for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
  79. mem_map[i].virt = pd[i].virt;
  80. mem_map[i].phys = pd[i].phys;
  81. mem_map[i].size = pd[i].size;
  82. mem_map[i].attrs = pd[i].attrs;
  83. }
  84. }
  85. static void rpi_update_mem_map(void)
  86. {
  87. int ret;
  88. struct mm_region *mm;
  89. const struct udevice_id *of_match = board_ids;
  90. while (of_match->compatible) {
  91. ret = fdt_node_check_compatible(gd->fdt_blob, 0,
  92. of_match->compatible);
  93. if (!ret) {
  94. mm = (struct mm_region *)of_match->data;
  95. _rpi_update_mem_map(mm);
  96. break;
  97. }
  98. of_match++;
  99. }
  100. }
  101. #else
  102. static void rpi_update_mem_map(void) {}
  103. #endif
  104. unsigned long rpi_bcm283x_base = 0x3f000000;
  105. int arch_cpu_init(void)
  106. {
  107. icache_enable();
  108. return 0;
  109. }
  110. int mach_cpu_init(void)
  111. {
  112. int ret, soc_offset;
  113. u64 io_base, size;
  114. rpi_update_mem_map();
  115. /* Get IO base from device tree */
  116. soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
  117. if (soc_offset < 0)
  118. return soc_offset;
  119. ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
  120. &io_base, &size);
  121. if (ret)
  122. return ret;
  123. rpi_bcm283x_base = io_base;
  124. return 0;
  125. }
  126. #ifdef CONFIG_ARMV7_LPAE
  127. #ifdef CONFIG_TARGET_RPI_4_32B
  128. #define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
  129. #include <addr_map.h>
  130. #include <asm/system.h>
  131. void init_addr_map(void)
  132. {
  133. mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
  134. BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  135. BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
  136. DCACHE_OFF);
  137. /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
  138. addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
  139. /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
  140. addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
  141. BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  142. BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
  143. }
  144. #endif
  145. void enable_caches(void)
  146. {
  147. dcache_enable();
  148. }
  149. #endif