timer.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2013
  8. * Bo Shen <voice.shen@atmel.com>
  9. */
  10. #include <common.h>
  11. #include <init.h>
  12. #include <time.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/at91_pit.h>
  17. #include <asm/arch/clk.h>
  18. #include <div64.h>
  19. #if !defined(CONFIG_AT91FAMILY)
  20. # error You need to define CONFIG_AT91FAMILY in your board config!
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /*
  24. * We're using the SAMA5D3x PITC in 32 bit mode, by
  25. * setting the 20 bit counter period to its maximum (0xfffff).
  26. * (See the relevant data sheets to understand that this really works)
  27. *
  28. * We do also mimic the typical powerpc way of incrementing
  29. * two 32 bit registers called tbl and tbu.
  30. *
  31. * Those registers increment at 1/16 the main clock rate.
  32. */
  33. #define TIMER_LOAD_VAL 0xfffff
  34. /*
  35. * Use the PITC in full 32 bit incrementing mode
  36. */
  37. int timer_init(void)
  38. {
  39. at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
  40. /* Enable PITC Clock */
  41. at91_periph_clk_enable(ATMEL_ID_PIT);
  42. /* Enable PITC */
  43. writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  44. gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
  45. return 0;
  46. }
  47. /*
  48. * Return the number of timer ticks per second.
  49. */
  50. ulong get_tbclk(void)
  51. {
  52. return gd->arch.timer_rate_hz;
  53. }