clock.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  4. *
  5. * Copyright (C) 2005 David Brownell
  6. * Copyright (C) 2005 Ivan Kokshaysky
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
  9. * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
  10. */
  11. #include <common.h>
  12. #include <asm/global_data.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/at91_pmc.h>
  18. #include <asm/arch/clk.h>
  19. #if !defined(CONFIG_AT91FAMILY)
  20. # error You need to define CONFIG_AT91FAMILY in your board config!
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static unsigned long at91_css_to_rate(unsigned long css)
  24. {
  25. switch (css) {
  26. case AT91_PMC_MCKR_CSS_SLOW:
  27. return CONFIG_SYS_AT91_SLOW_CLOCK;
  28. case AT91_PMC_MCKR_CSS_MAIN:
  29. return gd->arch.main_clk_rate_hz;
  30. case AT91_PMC_MCKR_CSS_PLLA:
  31. return gd->arch.plla_rate_hz;
  32. }
  33. return 0;
  34. }
  35. static u32 at91_pll_rate(u32 freq, u32 reg)
  36. {
  37. unsigned mul, div;
  38. div = reg & 0xff;
  39. mul = (reg >> 18) & 0x7f;
  40. if (div && mul) {
  41. freq /= div;
  42. freq *= mul + 1;
  43. } else {
  44. freq = 0;
  45. }
  46. return freq;
  47. }
  48. int at91_clock_init(unsigned long main_clock)
  49. {
  50. unsigned freq, mckr;
  51. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  52. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  53. unsigned tmp;
  54. /*
  55. * When the bootloader initialized the main oscillator correctly,
  56. * there's no problem using the cycle counter. But if it didn't,
  57. * or when using oscillator bypass mode, we must be told the speed
  58. * of the main clock.
  59. */
  60. if (!main_clock) {
  61. do {
  62. tmp = readl(&pmc->mcfr);
  63. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  64. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  65. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  66. }
  67. #endif
  68. gd->arch.main_clk_rate_hz = main_clock;
  69. /* report if PLLA is more than mildly overclocked */
  70. gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  71. /*
  72. * MCK and CPU derive from one of those primary clocks.
  73. * For now, assume this parentage won't change.
  74. */
  75. mckr = readl(&pmc->mckr);
  76. /* plla divisor by 2 */
  77. if (mckr & (1 << 12))
  78. gd->arch.plla_rate_hz >>= 1;
  79. gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  80. freq = gd->arch.mck_rate_hz;
  81. /* prescale */
  82. freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
  83. switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
  84. case AT91_PMC_MCKR_MDIV_2:
  85. gd->arch.mck_rate_hz = freq / 2;
  86. break;
  87. case AT91_PMC_MCKR_MDIV_3:
  88. gd->arch.mck_rate_hz = freq / 3;
  89. break;
  90. case AT91_PMC_MCKR_MDIV_4:
  91. gd->arch.mck_rate_hz = freq / 4;
  92. break;
  93. default:
  94. break;
  95. }
  96. gd->arch.cpu_clk_rate_hz = freq;
  97. return 0;
  98. }
  99. void at91_plla_init(u32 pllar)
  100. {
  101. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  102. writel(pllar, &pmc->pllar);
  103. while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
  104. ;
  105. }
  106. void at91_mck_init(u32 mckr)
  107. {
  108. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  109. u32 tmp;
  110. tmp = readl(&pmc->mckr);
  111. tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
  112. AT91_PMC_MCKR_PRES_MASK |
  113. AT91_PMC_MCKR_MDIV_MASK |
  114. AT91_PMC_MCKR_PLLADIV_2);
  115. #ifdef CPU_HAS_H32MXDIV
  116. tmp &= ~AT91_PMC_MCKR_H32MXDIV;
  117. #endif
  118. tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
  119. AT91_PMC_MCKR_PRES_MASK |
  120. AT91_PMC_MCKR_MDIV_MASK |
  121. AT91_PMC_MCKR_PLLADIV_2);
  122. #ifdef CPU_HAS_H32MXDIV
  123. tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
  124. #endif
  125. writel(tmp, &pmc->mckr);
  126. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  127. ;
  128. }
  129. /*
  130. * For the Master Clock Controller Register(MCKR), while switching
  131. * to a lower clock source, we must switch the clock source first
  132. * instead of last. Otherwise, we could end up with too high frequency
  133. * on the internal bus and peripherals.
  134. */
  135. void at91_mck_init_down(u32 mckr)
  136. {
  137. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  138. u32 tmp;
  139. tmp = readl(&pmc->mckr);
  140. tmp &= (~AT91_PMC_MCKR_CSS_MASK);
  141. tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
  142. writel(tmp, &pmc->mckr);
  143. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  144. ;
  145. #ifdef CPU_HAS_H32MXDIV
  146. tmp = readl(&pmc->mckr);
  147. tmp &= (~AT91_PMC_MCKR_H32MXDIV);
  148. tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
  149. writel(tmp, &pmc->mckr);
  150. #endif
  151. tmp = readl(&pmc->mckr);
  152. tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
  153. tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
  154. writel(tmp, &pmc->mckr);
  155. tmp = readl(&pmc->mckr);
  156. tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
  157. tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
  158. writel(tmp, &pmc->mckr);
  159. tmp = readl(&pmc->mckr);
  160. tmp &= (~AT91_PMC_MCKR_PRES_MASK);
  161. tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
  162. writel(tmp, &pmc->mckr);
  163. }
  164. int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
  165. {
  166. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  167. u32 regval, status;
  168. u32 timeout = 1000;
  169. if (id > AT91_PMC_PCR_PID_MASK)
  170. return -EINVAL;
  171. if (div > 0xff)
  172. return -EINVAL;
  173. if (clk_source == GCK_CSS_UPLL_CLK) {
  174. if (at91_upll_clk_enable())
  175. return -ENODEV;
  176. }
  177. writel(id, &pmc->pcr);
  178. regval = readl(&pmc->pcr);
  179. regval &= ~AT91_PMC_PCR_GCKCSS;
  180. regval &= ~AT91_PMC_PCR_GCKDIV;
  181. switch (clk_source) {
  182. case GCK_CSS_SLOW_CLK:
  183. regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
  184. break;
  185. case GCK_CSS_MAIN_CLK:
  186. regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
  187. break;
  188. case GCK_CSS_PLLA_CLK:
  189. regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
  190. break;
  191. case GCK_CSS_UPLL_CLK:
  192. regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
  193. break;
  194. case GCK_CSS_MCK_CLK:
  195. regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
  196. break;
  197. case GCK_CSS_AUDIO_CLK:
  198. regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
  199. break;
  200. default:
  201. printf("Error GCK clock source selection!\n");
  202. return -EINVAL;
  203. }
  204. regval |= AT91_PMC_PCR_CMD_WRITE |
  205. AT91_PMC_PCR_GCKDIV_(div) |
  206. AT91_PMC_PCR_GCKEN;
  207. writel(regval, &pmc->pcr);
  208. do {
  209. udelay(1);
  210. status = readl(&pmc->sr);
  211. } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
  212. if (!timeout)
  213. printf("Timeout waiting for GCK ready!\n");
  214. return 0;
  215. }
  216. u32 at91_get_periph_generated_clk(u32 id)
  217. {
  218. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  219. u32 regval, clk_source, div;
  220. u32 freq;
  221. if (id > AT91_PMC_PCR_PID_MASK)
  222. return 0;
  223. writel(id, &pmc->pcr);
  224. regval = readl(&pmc->pcr);
  225. clk_source = regval & AT91_PMC_PCR_GCKCSS;
  226. switch (clk_source) {
  227. case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
  228. freq = CONFIG_SYS_AT91_SLOW_CLOCK;
  229. break;
  230. case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
  231. freq = gd->arch.main_clk_rate_hz;
  232. break;
  233. case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
  234. freq = gd->arch.plla_rate_hz;
  235. break;
  236. case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
  237. freq = AT91_UTMI_PLL_CLK_FREQ;
  238. break;
  239. case AT91_PMC_PCR_GCKCSS_MCK_CLK:
  240. freq = gd->arch.mck_rate_hz;
  241. break;
  242. default:
  243. printf("Improper GCK clock source selection!\n");
  244. freq = 0;
  245. break;
  246. }
  247. div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
  248. div += 1;
  249. return freq / div;
  250. }