clock.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  4. *
  5. * Copyright (C) 2005 David Brownell
  6. * Copyright (C) 2005 Ivan Kokshaysky
  7. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. */
  9. #include <common.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/at91_pmc.h>
  14. #include <asm/arch/clk.h>
  15. #if !defined(CONFIG_AT91FAMILY)
  16. # error You need to define CONFIG_AT91FAMILY in your board config!
  17. #endif
  18. #define EN_PLLB_TIMEOUT 500
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static unsigned long at91_css_to_rate(unsigned long css)
  21. {
  22. switch (css) {
  23. case AT91_PMC_MCKR_CSS_SLOW:
  24. return CONFIG_SYS_AT91_SLOW_CLOCK;
  25. case AT91_PMC_MCKR_CSS_MAIN:
  26. return gd->arch.main_clk_rate_hz;
  27. case AT91_PMC_MCKR_CSS_PLLA:
  28. return gd->arch.plla_rate_hz;
  29. case AT91_PMC_MCKR_CSS_PLLB:
  30. return gd->arch.pllb_rate_hz;
  31. }
  32. return 0;
  33. }
  34. #ifdef CONFIG_USB_ATMEL
  35. static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  36. {
  37. unsigned i, div = 0, mul = 0, diff = 1 << 30;
  38. unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  39. /* PLL output max 240 MHz (or 180 MHz per errata) */
  40. if (out_freq > 240000000)
  41. goto fail;
  42. for (i = 1; i < 256; i++) {
  43. int diff1;
  44. unsigned input, mul1;
  45. /*
  46. * PLL input between 1MHz and 32MHz per spec, but lower
  47. * frequences seem necessary in some cases so allow 100K.
  48. * Warning: some newer products need 2MHz min.
  49. */
  50. input = main_freq / i;
  51. #if defined(CONFIG_AT91SAM9G20)
  52. if (input < 2000000)
  53. continue;
  54. #endif
  55. if (input < 100000)
  56. continue;
  57. if (input > 32000000)
  58. continue;
  59. mul1 = out_freq / input;
  60. #if defined(CONFIG_AT91SAM9G20)
  61. if (mul > 63)
  62. continue;
  63. #endif
  64. if (mul1 > 2048)
  65. continue;
  66. if (mul1 < 2)
  67. goto fail;
  68. diff1 = out_freq - input * mul1;
  69. if (diff1 < 0)
  70. diff1 = -diff1;
  71. if (diff > diff1) {
  72. diff = diff1;
  73. div = i;
  74. mul = mul1;
  75. if (diff == 0)
  76. break;
  77. }
  78. }
  79. if (i == 256 && diff > (out_freq >> 5))
  80. goto fail;
  81. return ret | ((mul - 1) << 16) | div;
  82. fail:
  83. return 0;
  84. }
  85. #endif
  86. static u32 at91_pll_rate(u32 freq, u32 reg)
  87. {
  88. unsigned mul, div;
  89. div = reg & 0xff;
  90. mul = (reg >> 16) & 0x7ff;
  91. if (div && mul) {
  92. freq /= div;
  93. freq *= mul + 1;
  94. } else
  95. freq = 0;
  96. return freq;
  97. }
  98. int at91_clock_init(unsigned long main_clock)
  99. {
  100. unsigned freq, mckr;
  101. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  102. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  103. unsigned tmp;
  104. /*
  105. * When the bootloader initialized the main oscillator correctly,
  106. * there's no problem using the cycle counter. But if it didn't,
  107. * or when using oscillator bypass mode, we must be told the speed
  108. * of the main clock.
  109. */
  110. if (!main_clock) {
  111. do {
  112. tmp = readl(&pmc->mcfr);
  113. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  114. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  115. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  116. }
  117. #endif
  118. gd->arch.main_clk_rate_hz = main_clock;
  119. /* report if PLLA is more than mildly overclocked */
  120. gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  121. #ifdef CONFIG_USB_ATMEL
  122. /*
  123. * USB clock init: choose 48 MHz PLLB value,
  124. * disable 48MHz clock during usb peripheral suspend.
  125. *
  126. * REVISIT: assumes MCK doesn't derive from PLLB!
  127. */
  128. gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
  129. AT91_PMC_PLLBR_USBDIV_2;
  130. gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
  131. gd->arch.at91_pllb_usb_init);
  132. #endif
  133. /*
  134. * MCK and CPU derive from one of those primary clocks.
  135. * For now, assume this parentage won't change.
  136. */
  137. mckr = readl(&pmc->mckr);
  138. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
  139. || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
  140. /* plla divisor by 2 */
  141. gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
  142. #endif
  143. gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  144. freq = gd->arch.mck_rate_hz;
  145. #if defined(CONFIG_AT91SAM9X5)
  146. /* different in prescale on at91sam9x5 */
  147. freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
  148. #else
  149. freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
  150. #endif
  151. #if defined(CONFIG_AT91SAM9G20)
  152. /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
  153. gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
  154. freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
  155. if (mckr & AT91_PMC_MCKR_MDIV_MASK)
  156. freq /= 2; /* processor clock division */
  157. #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
  158. || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
  159. /* mdiv <==> divisor
  160. * 0 <==> 1
  161. * 1 <==> 2
  162. * 2 <==> 4
  163. * 3 <==> 3
  164. */
  165. gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
  166. (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
  167. ? freq / 3
  168. : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
  169. #else
  170. gd->arch.mck_rate_hz = freq /
  171. (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
  172. #endif
  173. gd->arch.cpu_clk_rate_hz = freq;
  174. return 0;
  175. }
  176. #if !defined(AT91_PLL_LOCK_TIMEOUT)
  177. #define AT91_PLL_LOCK_TIMEOUT 1000000
  178. #endif
  179. void at91_plla_init(u32 pllar)
  180. {
  181. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  182. writel(pllar, &pmc->pllar);
  183. while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
  184. ;
  185. }
  186. void at91_pllb_init(u32 pllbr)
  187. {
  188. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  189. writel(pllbr, &pmc->pllbr);
  190. while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
  191. ;
  192. }
  193. void at91_mck_init(u32 mckr)
  194. {
  195. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  196. u32 tmp;
  197. tmp = readl(&pmc->mckr);
  198. tmp &= ~AT91_PMC_MCKR_PRES_MASK;
  199. tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
  200. writel(tmp, &pmc->mckr);
  201. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  202. ;
  203. tmp = readl(&pmc->mckr);
  204. tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
  205. tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
  206. writel(tmp, &pmc->mckr);
  207. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  208. ;
  209. tmp = readl(&pmc->mckr);
  210. tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
  211. tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
  212. writel(tmp, &pmc->mckr);
  213. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  214. ;
  215. tmp = readl(&pmc->mckr);
  216. tmp &= ~AT91_PMC_MCKR_CSS_MASK;
  217. tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
  218. writel(tmp, &pmc->mckr);
  219. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  220. ;
  221. }
  222. int at91_pllb_clk_enable(u32 pllbr)
  223. {
  224. struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  225. ulong start_time, tmp_time;
  226. start_time = get_timer(0);
  227. writel(pllbr, &pmc->pllbr);
  228. while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
  229. tmp_time = get_timer(0);
  230. if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  231. printf("ERROR: failed to enable PLLB\n");
  232. return -1;
  233. }
  234. }
  235. return 0;
  236. }
  237. int at91_pllb_clk_disable(void)
  238. {
  239. struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  240. ulong start_time, tmp_time;
  241. start_time = get_timer(0);
  242. writel(0, &pmc->pllbr);
  243. while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
  244. tmp_time = get_timer(0);
  245. if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  246. printf("ERROR: failed to disable PLLB\n");
  247. return -1;
  248. }
  249. }
  250. return 0;
  251. }