timer.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Lineo, Inc. <www.lineo.com>
  5. * Bernhard Kuhn <bkuhn@lineo.com>
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. *
  11. * (C) Copyright 2002
  12. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13. * Alex Zuepke <azu@sysgo.de>
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <time.h>
  18. #include <asm/global_data.h>
  19. #include <linux/delay.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/hardware.h>
  22. #include <asm/arch/at91_tc.h>
  23. #include <asm/arch/clk.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /* the number of clocks per CONFIG_SYS_HZ */
  26. #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
  27. int timer_init(void)
  28. {
  29. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  30. at91_periph_clk_enable(ATMEL_ID_TC0);
  31. writel(0, &tc->bcr);
  32. writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
  33. AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
  34. writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
  35. /* set to MCLK/2 and restart the timer
  36. when the value in TC_RC is reached */
  37. writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
  38. writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
  39. writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
  40. writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
  41. gd->arch.lastinc = 0;
  42. gd->arch.tbl = 0;
  43. return 0;
  44. }
  45. /*
  46. * timer without interrupts
  47. */
  48. ulong get_timer_raw(void)
  49. {
  50. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  51. u32 now;
  52. now = readl(&tc->tc[0].cv) & 0x0000ffff;
  53. if (now >= gd->arch.lastinc) {
  54. /* normal mode */
  55. gd->arch.tbl += now - gd->arch.lastinc;
  56. } else {
  57. /* we have an overflow ... */
  58. gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
  59. }
  60. gd->arch.lastinc = now;
  61. return gd->arch.tbl;
  62. }
  63. static ulong get_timer_masked(void)
  64. {
  65. return get_timer_raw()/TIMER_LOAD_VAL;
  66. }
  67. ulong get_timer(ulong base)
  68. {
  69. return get_timer_masked() - base;
  70. }
  71. void __udelay(unsigned long usec)
  72. {
  73. u32 tmo;
  74. u32 endtime;
  75. signed long diff;
  76. tmo = CONFIG_SYS_HZ_CLOCK / 1000;
  77. tmo *= usec;
  78. tmo /= 1000;
  79. endtime = get_timer_raw() + tmo;
  80. do {
  81. u32 now = get_timer_raw();
  82. diff = endtime - now;
  83. } while (diff >= 0);
  84. }
  85. /*
  86. * This function is derived from PowerPC code (read timebase as long long).
  87. * On ARM it just returns the timer value.
  88. */
  89. unsigned long long get_ticks(void)
  90. {
  91. return get_timer(0);
  92. }
  93. /*
  94. * This function is derived from PowerPC code (timebase clock frequency).
  95. * On ARM it returns the number of timer ticks per second.
  96. */
  97. ulong get_tbclk(void)
  98. {
  99. return CONFIG_SYS_HZ;
  100. }