clock.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
  4. *
  5. * Copyright (C) 2011 Andreas Bießmann
  6. * Copyright (C) 2005 David Brownell
  7. * Copyright (C) 2005 Ivan Kokshaysky
  8. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  9. */
  10. #include <common.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/at91_pmc.h>
  15. #include <asm/arch/clk.h>
  16. #if !defined(CONFIG_AT91FAMILY)
  17. # error You need to define CONFIG_AT91FAMILY in your board config!
  18. #endif
  19. #define EN_PLLB_TIMEOUT 500
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static unsigned long at91_css_to_rate(unsigned long css)
  22. {
  23. switch (css) {
  24. case AT91_PMC_MCKR_CSS_SLOW:
  25. return CONFIG_SYS_AT91_SLOW_CLOCK;
  26. case AT91_PMC_MCKR_CSS_MAIN:
  27. return gd->arch.main_clk_rate_hz;
  28. case AT91_PMC_MCKR_CSS_PLLA:
  29. return gd->arch.plla_rate_hz;
  30. case AT91_PMC_MCKR_CSS_PLLB:
  31. return gd->arch.pllb_rate_hz;
  32. }
  33. return 0;
  34. }
  35. #ifdef CONFIG_USB_ATMEL
  36. static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  37. {
  38. unsigned i, div = 0, mul = 0, diff = 1 << 30;
  39. unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  40. /* PLL output max 240 MHz (or 180 MHz per errata) */
  41. if (out_freq > 240000000)
  42. goto fail;
  43. for (i = 1; i < 256; i++) {
  44. int diff1;
  45. unsigned input, mul1;
  46. /*
  47. * PLL input between 1MHz and 32MHz per spec, but lower
  48. * frequences seem necessary in some cases so allow 100K.
  49. * Warning: some newer products need 2MHz min.
  50. */
  51. input = main_freq / i;
  52. if (input < 100000)
  53. continue;
  54. if (input > 32000000)
  55. continue;
  56. mul1 = out_freq / input;
  57. if (mul1 > 2048)
  58. continue;
  59. if (mul1 < 2)
  60. goto fail;
  61. diff1 = out_freq - input * mul1;
  62. if (diff1 < 0)
  63. diff1 = -diff1;
  64. if (diff > diff1) {
  65. diff = diff1;
  66. div = i;
  67. mul = mul1;
  68. if (diff == 0)
  69. break;
  70. }
  71. }
  72. if (i == 256 && diff > (out_freq >> 5))
  73. goto fail;
  74. return ret | ((mul - 1) << 16) | div;
  75. fail:
  76. return 0;
  77. }
  78. #endif
  79. static u32 at91_pll_rate(u32 freq, u32 reg)
  80. {
  81. unsigned mul, div;
  82. div = reg & 0xff;
  83. mul = (reg >> 16) & 0x7ff;
  84. if (div && mul) {
  85. freq /= div;
  86. freq *= mul + 1;
  87. } else
  88. freq = 0;
  89. return freq;
  90. }
  91. int at91_clock_init(unsigned long main_clock)
  92. {
  93. unsigned freq, mckr;
  94. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  95. #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
  96. unsigned tmp;
  97. /*
  98. * When the bootloader initialized the main oscillator correctly,
  99. * there's no problem using the cycle counter. But if it didn't,
  100. * or when using oscillator bypass mode, we must be told the speed
  101. * of the main clock.
  102. */
  103. if (!main_clock) {
  104. do {
  105. tmp = readl(&pmc->mcfr);
  106. } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
  107. tmp &= AT91_PMC_MCFR_MAINF_MASK;
  108. main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
  109. }
  110. #endif
  111. gd->arch.main_clk_rate_hz = main_clock;
  112. /* report if PLLA is more than mildly overclocked */
  113. gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
  114. #ifdef CONFIG_USB_ATMEL
  115. /*
  116. * USB clock init: choose 48 MHz PLLB value,
  117. * disable 48MHz clock during usb peripheral suspend.
  118. *
  119. * REVISIT: assumes MCK doesn't derive from PLLB!
  120. */
  121. gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
  122. AT91_PMC_PLLBR_USBDIV_2;
  123. gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
  124. gd->arch.at91_pllb_usb_init);
  125. #endif
  126. /*
  127. * MCK and CPU derive from one of those primary clocks.
  128. * For now, assume this parentage won't change.
  129. */
  130. mckr = readl(&pmc->mckr);
  131. gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
  132. freq = gd->arch.mck_rate_hz;
  133. freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
  134. /* mdiv */
  135. gd->arch.mck_rate_hz = freq /
  136. (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
  137. gd->arch.cpu_clk_rate_hz = freq;
  138. return 0;
  139. }
  140. int at91_pllb_clk_enable(u32 pllbr)
  141. {
  142. struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  143. ulong start_time, tmp_time;
  144. start_time = get_timer(0);
  145. writel(pllbr, &pmc->pllbr);
  146. while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
  147. tmp_time = get_timer(0);
  148. if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  149. printf("ERROR: failed to enable PLLB\n");
  150. return -1;
  151. }
  152. }
  153. return 0;
  154. }
  155. int at91_pllb_clk_disable(void)
  156. {
  157. struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  158. ulong start_time, tmp_time;
  159. start_time = get_timer(0);
  160. writel(0, &pmc->pllbr);
  161. while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
  162. tmp_time = get_timer(0);
  163. if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  164. printf("ERROR: failed to disable PLLB\n");
  165. return -1;
  166. }
  167. }
  168. return 0;
  169. }