cache.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /* for now: just dummy functions to satisfy the linker */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <asm/cache.h>
  12. #include <asm/global_data.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /*
  15. * Flush range from all levels of d-cache/unified-cache.
  16. * Affects the range [start, start + size - 1].
  17. */
  18. __weak void flush_cache(unsigned long start, unsigned long size)
  19. {
  20. flush_dcache_range(start, start + size);
  21. }
  22. /*
  23. * Default implementation:
  24. * do a range flush for the entire range
  25. */
  26. __weak void flush_dcache_all(void)
  27. {
  28. flush_cache(0, ~0);
  29. }
  30. /*
  31. * Default implementation of enable_caches()
  32. * Real implementation should be in platform code
  33. */
  34. __weak void enable_caches(void)
  35. {
  36. puts("WARNING: Caches not enabled\n");
  37. }
  38. __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
  39. {
  40. /* An empty stub, real implementation should be in platform code */
  41. }
  42. __weak void flush_dcache_range(unsigned long start, unsigned long stop)
  43. {
  44. /* An empty stub, real implementation should be in platform code */
  45. }
  46. int check_cache_range(unsigned long start, unsigned long stop)
  47. {
  48. int ok = 1;
  49. if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
  50. ok = 0;
  51. if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
  52. ok = 0;
  53. if (!ok) {
  54. warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
  55. start, stop);
  56. }
  57. return ok;
  58. }
  59. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  60. /*
  61. * Reserve one MMU section worth of address space below the malloc() area that
  62. * will be mapped uncached.
  63. */
  64. static unsigned long noncached_start;
  65. static unsigned long noncached_end;
  66. static unsigned long noncached_next;
  67. void noncached_set_region(void)
  68. {
  69. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  70. mmu_set_region_dcache_behaviour(noncached_start,
  71. noncached_end - noncached_start,
  72. DCACHE_OFF);
  73. #endif
  74. }
  75. int noncached_init(void)
  76. {
  77. phys_addr_t start, end;
  78. size_t size;
  79. /* If this calculation changes, update board_f.c:reserve_noncached() */
  80. end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
  81. size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
  82. start = end - size;
  83. debug("mapping memory %pa-%pa non-cached\n", &start, &end);
  84. noncached_start = start;
  85. noncached_end = end;
  86. noncached_next = start;
  87. noncached_set_region();
  88. return 0;
  89. }
  90. phys_addr_t noncached_alloc(size_t size, size_t align)
  91. {
  92. phys_addr_t next = ALIGN(noncached_next, align);
  93. if (next >= noncached_end || (noncached_end - next) < size)
  94. return 0;
  95. debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
  96. noncached_next = next + size;
  97. return next;
  98. }
  99. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  100. #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
  101. void invalidate_l2_cache(void)
  102. {
  103. unsigned int val = 0;
  104. asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
  105. : : "r" (val) : "cc");
  106. isb();
  107. }
  108. #endif
  109. int arch_reserve_mmu(void)
  110. {
  111. return arm_reserve_mmu();
  112. }
  113. __weak int arm_reserve_mmu(void)
  114. {
  115. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  116. /* reserve TLB table */
  117. gd->arch.tlb_size = PGTABLE_SIZE;
  118. gd->relocaddr -= gd->arch.tlb_size;
  119. /* round down to next 64 kB limit */
  120. gd->relocaddr &= ~(0x10000 - 1);
  121. gd->arch.tlb_addr = gd->relocaddr;
  122. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  123. gd->arch.tlb_addr + gd->arch.tlb_size);
  124. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  125. /*
  126. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  127. * with location within secure ram.
  128. */
  129. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  130. #endif
  131. #endif
  132. return 0;
  133. }