cache-cp15.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <log.h>
  9. #include <asm/global_data.h>
  10. #include <asm/system.h>
  11. #include <asm/cache.h>
  12. #include <linux/compiler.h>
  13. #include <asm/armv7_mpu.h>
  14. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #ifdef CONFIG_SYS_ARM_MMU
  17. __weak void arm_init_before_mmu(void)
  18. {
  19. }
  20. __weak void arm_init_domains(void)
  21. {
  22. }
  23. static void set_section_phys(int section, phys_addr_t phys,
  24. enum dcache_option option)
  25. {
  26. #ifdef CONFIG_ARMV7_LPAE
  27. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  28. /* Need to set the access flag to not fault */
  29. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  30. #else
  31. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  32. u32 value = TTB_SECT_AP;
  33. #endif
  34. /* Add the page offset */
  35. value |= phys;
  36. /* Add caching bits */
  37. value |= option;
  38. /* Set PTE */
  39. page_table[section] = value;
  40. }
  41. void set_section_dcache(int section, enum dcache_option option)
  42. {
  43. set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
  44. }
  45. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  46. {
  47. debug("%s: Warning: not implemented\n", __func__);
  48. }
  49. void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
  50. size_t size, enum dcache_option option)
  51. {
  52. #ifdef CONFIG_ARMV7_LPAE
  53. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  54. #else
  55. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  56. #endif
  57. unsigned long startpt, stoppt;
  58. unsigned long upto, end;
  59. /* div by 2 before start + size to avoid phys_addr_t overflow */
  60. end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
  61. >> (MMU_SECTION_SHIFT - 1);
  62. start = start >> MMU_SECTION_SHIFT;
  63. #ifdef CONFIG_ARMV7_LPAE
  64. debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  65. option);
  66. #else
  67. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  68. option);
  69. #endif
  70. for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
  71. set_section_phys(upto, phys, option);
  72. /*
  73. * Make sure range is cache line aligned
  74. * Only CPU maintains page tables, hence it is safe to always
  75. * flush complete cache lines...
  76. */
  77. startpt = (unsigned long)&page_table[start];
  78. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  79. stoppt = (unsigned long)&page_table[end];
  80. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  81. mmu_page_table_flush(startpt, stoppt);
  82. }
  83. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  84. enum dcache_option option)
  85. {
  86. mmu_set_region_dcache_behaviour_phys(start, start, size, option);
  87. }
  88. __weak void dram_bank_mmu_setup(int bank)
  89. {
  90. struct bd_info *bd = gd->bd;
  91. int i;
  92. /* bd->bi_dram is available only after relocation */
  93. if ((gd->flags & GD_FLG_RELOC) == 0)
  94. return;
  95. debug("%s: bank: %d\n", __func__, bank);
  96. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  97. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  98. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  99. i++)
  100. set_section_dcache(i, DCACHE_DEFAULT_OPTION);
  101. }
  102. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  103. static inline void mmu_setup(void)
  104. {
  105. int i;
  106. u32 reg;
  107. arm_init_before_mmu();
  108. /* Set up an identity-mapping for all 4GB, rw for everyone */
  109. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  110. set_section_dcache(i, DCACHE_OFF);
  111. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  112. dram_bank_mmu_setup(i);
  113. }
  114. #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
  115. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  116. for (i = 0; i < 4; i++) {
  117. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  118. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  119. page_table[i] = tpt | TTB_PAGETABLE;
  120. }
  121. reg = TTBCR_EAE;
  122. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  123. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  124. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  125. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  126. #else
  127. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  128. #endif
  129. if (is_hyp()) {
  130. /* Set HTCR to enable LPAE */
  131. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  132. : : "r" (reg) : "memory");
  133. /* Set HTTBR0 */
  134. asm volatile("mcrr p15, 4, %0, %1, c2"
  135. :
  136. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  137. : "memory");
  138. /* Set HMAIR */
  139. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  140. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  141. } else {
  142. /* Set TTBCR to enable LPAE */
  143. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  144. : : "r" (reg) : "memory");
  145. /* Set 64-bit TTBR0 */
  146. asm volatile("mcrr p15, 0, %0, %1, c2"
  147. :
  148. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  149. : "memory");
  150. /* Set MAIR */
  151. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  152. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  153. }
  154. #elif defined(CONFIG_CPU_V7A)
  155. if (is_hyp()) {
  156. /* Set HTCR to disable LPAE */
  157. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  158. : : "r" (0) : "memory");
  159. } else {
  160. /* Set TTBCR to disable LPAE */
  161. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  162. : : "r" (0) : "memory");
  163. }
  164. /* Set TTBR0 */
  165. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  166. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  167. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  168. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  169. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  170. #else
  171. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  172. #endif
  173. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  174. : : "r" (reg) : "memory");
  175. #else
  176. /* Copy the page table address to cp15 */
  177. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  178. : : "r" (gd->arch.tlb_addr) : "memory");
  179. #endif
  180. /* Set the access control to all-supervisor */
  181. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  182. : : "r" (~0));
  183. arm_init_domains();
  184. /* and enable the mmu */
  185. reg = get_cr(); /* get control reg. */
  186. set_cr(reg | CR_M);
  187. }
  188. static int mmu_enabled(void)
  189. {
  190. return get_cr() & CR_M;
  191. }
  192. #endif /* CONFIG_SYS_ARM_MMU */
  193. /* cache_bit must be either CR_I or CR_C */
  194. static void cache_enable(uint32_t cache_bit)
  195. {
  196. uint32_t reg;
  197. /* The data cache is not active unless the mmu/mpu is enabled too */
  198. #ifdef CONFIG_SYS_ARM_MMU
  199. if ((cache_bit == CR_C) && !mmu_enabled())
  200. mmu_setup();
  201. #elif defined(CONFIG_SYS_ARM_MPU)
  202. if ((cache_bit == CR_C) && !mpu_enabled()) {
  203. printf("Consider enabling MPU before enabling caches\n");
  204. return;
  205. }
  206. #endif
  207. reg = get_cr(); /* get control reg. */
  208. set_cr(reg | cache_bit);
  209. }
  210. /* cache_bit must be either CR_I or CR_C */
  211. static void cache_disable(uint32_t cache_bit)
  212. {
  213. uint32_t reg;
  214. reg = get_cr();
  215. if (cache_bit == CR_C) {
  216. /* if cache isn;t enabled no need to disable */
  217. if ((reg & CR_C) != CR_C)
  218. return;
  219. #ifdef CONFIG_SYS_ARM_MMU
  220. /* if disabling data cache, disable mmu too */
  221. cache_bit |= CR_M;
  222. #endif
  223. }
  224. reg = get_cr();
  225. #ifdef CONFIG_SYS_ARM_MMU
  226. if (cache_bit == (CR_C | CR_M))
  227. #elif defined(CONFIG_SYS_ARM_MPU)
  228. if (cache_bit == CR_C)
  229. #endif
  230. flush_dcache_all();
  231. set_cr(reg & ~cache_bit);
  232. }
  233. #endif
  234. #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  235. void icache_enable(void)
  236. {
  237. return;
  238. }
  239. void icache_disable(void)
  240. {
  241. return;
  242. }
  243. int icache_status(void)
  244. {
  245. return 0; /* always off */
  246. }
  247. #else
  248. void icache_enable(void)
  249. {
  250. cache_enable(CR_I);
  251. }
  252. void icache_disable(void)
  253. {
  254. cache_disable(CR_I);
  255. }
  256. int icache_status(void)
  257. {
  258. return (get_cr() & CR_I) != 0;
  259. }
  260. #endif
  261. #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  262. void dcache_enable(void)
  263. {
  264. return;
  265. }
  266. void dcache_disable(void)
  267. {
  268. return;
  269. }
  270. int dcache_status(void)
  271. {
  272. return 0; /* always off */
  273. }
  274. #else
  275. void dcache_enable(void)
  276. {
  277. cache_enable(CR_C);
  278. }
  279. void dcache_disable(void)
  280. {
  281. cache_disable(CR_C);
  282. }
  283. int dcache_status(void)
  284. {
  285. return (get_cr() & CR_C) != 0;
  286. }
  287. #endif